Memory Organization
1. Any electronic holding place where data can be stored and retrieved later whenever required is ____________
a) memory
b) drive
c) disk
d) circuit
Explanation: Memory is the place where data can be stored and later retrieved. Memory can be of classified into register, cache, main memory, etc.
2. Cache memory is the onboard storage.
a) True
b) False
Explanation: Cache Memory is the memory closest to the CPU. Registers, Cache and the main memory are the means of onboard storage in the computer system.
3. Which of the following is the fastest means of memory access for CPU?
a) Registers
b) Cache
c) Main memory
d) Virtual Memory
Explanation: Registers are the fastest means of access for CPU. Registers are the small memory locations which are present closest to the CPU.
4. The memory implemented using the semiconductor chips is _________
a) Cache
b) Main
c) Secondary
d) Registers
Explanation: The main memory is implemented using semiconductor chips. Main memory is located on the motherboard. It mainly consists of RAM and small amount of ROM.
5. Size of the ________ memory mainly depends on the size of the address bus.
a) Main
b) Virtual
c) Secondary
d) Cache
Explanation: The size of the main memory depends on the size of the address bus of the CPU. The main memory mainly consists of RAM and ROM, where RAM contains the current data and programs and ROM contains permanent programs like BIOS.
6. Which of the following is independent of the address bus?
a) Secondary memory
b) Main memory
c) Onboard memory
d) Cache memory
Explanation: The secondary memory is independent of the address bus. It increases the storage space. It is implemented in the form of magnetic storage devices.
7. ____________ storage is a system where a robotic arm will connect or disconnect off-line mass storage media according to the computer operating system demands.
a) Secondary
b) Virtual
c) Tertiary
d) Magnetic
Explanation: The tertiary storage is the correct option. It is used in the realms of enterprise storage and scientific computing on large computer systems and business computer networks and is something a typical personal computer never sees firsthand.
8. What is the location of the internal registers of CPU?
a) Internal
b) On-chip
c) External
d) Motherboard
9. MAR stands for ___________
a) Memory address register
b) Main address register
c) Main accessible register
d) Memory accessible register
Explanation: The MAR stands for memory address register. It holds the address of the active memory location.
10. If M denotes the number of memory locations and N denotes the word size, then an expression that denotes the storage capacity is ______________
a) M*N
b) M+N
c) 2M+N
d) 2M-N
Answer: a
Explanation: Storage capacity is the product of a number of memory locations that is the number of words and the word size or the number of bits stored per location. Storage capacity should be as large as possible.
11. What is the high speed memory between the main memory and the CPU called?
a) Register Memory
b) Cache Memory
c) Storage Memory
d) Virtual Memory
Explanation: It is called the Cache Memory. The cache memory is the high speed memory between the main memory and the CPU.
12. Cache Memory is implemented using the DRAM chips.
a) True
b) False
Answer: b
Explanation: The Cache memory is implemented using the SRAM chips and not the DRAM chips. SRAM stands for Static RAM. It is faster and is expensive.
13. Whenever the data is found in the cache memory it is called as _________
a) HIT
b) MISS
c) FOUND
d) ERROR
Explanation: Whenever the data is found in the cache memory, it is called as Cache HIT. CPU first checks in the cache memory since it is closest to the CPU.
14. LRU stands for ___________
a) Low Rate Usage
b) Least Rate Usage
c) Least Recently Used
d) Low Required Usage
Answer: c
Explanation: LRU stands for Least Recently Used. LRU is a type of replacement policy used by the cache memory.
15. When the data at a location in cache is different from the data located in the main memory, the cache is called _____________
a) Unique
b) Inconsistent
c) Variable
d) Fault
Answer: b
Explanation: The cache is said to be inconsistent. Inconsistency must be avoided as it leads to serious data bugs.
16. Which of the following is not a write policy to avoid Cache Coherence?
a) Write through
b) Write within
c) Write back
d) Buffered write
Answer: b
Explanation: There is no policy which is called as the write within policy. The other three options are the write policies which are used to avoid cache coherence.
17. Which of the following is an efficient method of cache updating?
a) Snoopy writes
b) Write through
c) Write within
d) Buffered write
Answer: a
Explanation: Snoopy writes is the efficient method for updating the cache. In this case, the cache controller snoops or monitors the operations of other bus masters.
18. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.
a) Associative
b) Direct
c) Set Associative
d) Indirect
Answer: a
Explanation: This happens in the associative mapping. In this case, a block of data from the main memory can be mapped anywhere in the cache memory.
19. The number of sign bits in a 32-bit IEEE format is ____
a) 1
b) 11
c) 9
d) 23
Answer: a
Explanation: There is only 1 sign bit in all the standards. In a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.
20. The transfer between CPU and Cache is ______________
a) Block transfer
b) Word transfer
c) Set transfer
d) Associative transfe
Explanation: The transfer is a word transfer. In the memory subsystem, word is transferred over the memory data bus and it typically has a width of a word or half-word.
Labels: COA MCQ's
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