1. If an interrupt is generated from outside the processor then it is an
a) internal interrupt
b) external interrupt
c) interrupt
d) none of the mentioned
Answer: b
Explanation: If an external device or a signal
interrupts the processor from outside then it is an external interrupt.
2. If the interrupt is generated by the execution of
an interrupt instruction then it is
a) internal interrupt
b) external interrupt
c) interrupt-in-interrupt
d) none of the mentioned
Answer: a
Explanation: The internal interrupt is generated
internally by the processor circuit or by the execution of an interrupt
instruction.
3. Example of an external interrupt is
a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
Answer: b
Explanation: Since the keyboard is external to the
processor, it is an external interrupt.
4. Example of an internal interrupt is
a) divide by zero interrupt
b) overflow interrupt
c) interrupt due to INT
d) all of the mentioned
Answer: d
Explanation: Since the interrupts occur within the
processor itself, they are called internal interrupts.
5. The interrupt request that is independent of IF
flag is
a) NMI
b) TRAP
c) Divide by zero
d) All of the mentioned
Answer: d
Explanation: These requests are independent of IF
flag.
6. The type of the interrupt may be passed to the
interrupt structure of CPU from
a) interrupt service routine
b) stack
c) interrupt controller
d) none of the mentioned
Answer: c
Explanation: After an interrupt is acknowledged, the
CPU computes the vector address from the type of the interrupt that may be
passed to the internal structure of the CPU from an interrupt controller in
case of external interrupts.
7. During the execution of an interrupt, the data
pushed into the stack is the content of
a) IP
b) CS
c) PSW
d) All of the mentioned
Answer: d
Explanation: The contents of IP, CS and PSW are pushed
into the stack during the execution.
8. After every response to the single step interrupt
the flag that is cleared is
a) IF (Interrupt Flag)
b) TF (Trap Flag)
c) OF (Overflow Flag)
d) None of the mentioned
Answer: b
Explanation: If the trap flag is set then the
processor enters the single step execution mode. After the execution, the trap
flag is cleared.
9. At the end of ISR, the instruction should be
a) END
b) ENDS
c) IRET
d) INTR
Answer: c
Explanation: After the execution of the ISR, the
control must go to the previous program (maybe main program) which was being
executed. To execute it, IRET is placed at the end of ISR.
10. When the CPU executes IRET,
a) contents of IP and CS are retrieved
b) the control transfers from ISR to main program
c) clears the trap flag
d) clears the interrupt flag
Answer: a
Explanation: When the instruction IRET is executed,
the contents of flags, IP and CS which were saved at the stack by the CALL
instruction are retrieved to the respective registers.
11. The number of hardware interrupts that the
processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
Answer: c
Explanation: The processor 8085 has five hardware
interrupt pins. Out of these five, four pins were alloted fixed vector
addresses but the pin INTR was not alloted by vector address, rather an
external device was supposed to hand over the type of the interrupt to the
microprocessor.
12. The register that stores all the interrupt
requests in it in order to serve them one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
Answer: a
Explanation: The interrupts at IRQ input lines are
handled by Interrupt Request Register internally.
13. The register that stores the bits required to mask
the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
Answer: c
Explanation: Also, Interrupt Mask Register operates on
IRR(Interrupt Request Register) at the direction of the Priority Resolver.
14. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Answer: d
Explanation: The interrupt control logic performs all
the operations that are involved within the interrupts like accepting and
managing interrupt acknowledge signals, interrupts.
15. In a cascaded mode, the number of vectored
interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
Answer: d
Explanation: A single 8259A provides 8 vectored
interrupts. In cascade mode, 64 vectored interrupts can be provided.
16. When the PS(active low)/EN(active low) pin of
8259A used in buffered mode, then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Answer: b
Explanation: When the pin is used in buffered mode,
then it can be used as a buffer enable to control buffer transreceivers. If it
is not used in buffered mode, then the pin is used as input to designate
whether the chip is used as a master or a slave.
17. Once the ICW1 is loaded, then the initialization
procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Answer: d
Explanation: The initialization procedure involves
i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is
set to IRR.
18. When non-specific EOI command is issued to 8259A
it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Answer: b
Explanation: When non-specific EOI command is issued
to 8259A it will automatically reset the highest ISR.
19. In the application where all the interrupting
devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
Answer: a
Explanation: The automatic rotation is used in the
applications where all the interrupting devices are of equal priority.
20. Programmable peripheral input-output port is
another name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
Answer: b
Explanation: The parallel input-output port chip 8255
is also known as programmable peripheral input-output port.
21. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports
Answer: c
Explanation: Port C can function independently either
as input or as output ports.
22. All the functions of the ports of 8255 are
achieved by programming the bits of an internal register called
a) data bus control
b) read logic control
c) control word register
d) none of the mentioned
Answer: c
Explanation: By programming the bits of control word
register, the operations of the ports are specified.
23. The data bus buffer is controlled by
a) control word register
b) read/write control logic
c) data bus
d) none of the mentioned
Answer: b
Explanation: The data bus buffer is controlled by
read/write control logic.
24. The input provided by the microprocessor to the
read/write control logic is
a) RESET
b) A1
c) WR(ACTIVE LOW)
d) All of the mentioned
Answer: d
Explanation: RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0,
RESET are the inputs provided by the microprocessor to the read/write control
logic of 8255.
25. The device that receives or transmits data upon
the execution of input or output instructions by the microprocessor is
a) control word register
b) read/write control logic
c) 3-state bidirectional buffer
d) none of the mentioned
Answer: c
Explanation: 3-state bidirectional buffer is used to
receives or transmits data upon the execution of input or output instructions
by the microprocessor.
26. The port that is used for the generation of
handshake lines in mode 1 or mode 2 is
a) port A
b) port B
c) port C Lower
d) port C Upper
Answer: d
Explanation: Port C upper is used for the generation
of handshake lines in mode 1 or mode 2.
27. If A1=0, A0=1 then the input read cycle is
performed from
a) port A to data bus
b) port B to data bus
c) port C to data bus
d) CWR to data bus
Answer: b
Explanation: If A1=0, A0=1 then the input read cycle
is performed from port B to data bus.
28. The function, ‘data bus tristated’ is performed
when
a) CS(active low) = 1
b) CS(active low) = 0
c) CS(active low) = 0, RD(active low) = 1, WR(active
low) = 1
d) CS(active low) = 1 OR CS(active low) = 0, RD(active
low) = 1, WR(active low) = 1
Answer: d
Explanation: The data bus is tristated when chip
select pin=1 or chip select pin=0 and read and write signals are high i.e 1.
29. The pin that clears the control word register of
8255 when enabled is
a) CLEAR
b) SET
c) RESET
d) CLK
Answer: c
Explanation: If reset pin is enabled then the control
word register is cleared.
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