Peripherals and their Interfacing with 8086

1. The number of counters that are present in the programmable timer device 8254 is

a) 1

b) 2

c) 3

d) 4

Answer: c

Explanation: There are three counters that can be used as either counters or delay generators.

 

2. The operation that can be performed on control word register is

a) read operation

b) write operation

c) read and write operations

d) none

Answer: b

Explanation: The control word register can only be written and cannot be read.

 

3. The mode that is used to interrupt the processor by setting a suitable terminal count is

a) mode 0

b) mode 1

c) mode 2

d) mode 3

Answer: a

Explanation: Mode 0 is also called as an interrupt on the terminal count.

 

4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low for

a) 1 clockcycle

b) 2 clockcycles

c) 3 clockcycles

d) 4 clockcycles

Answer: a

Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If the count N is reloaded and again the output becomes high and remains so for (N-1) clock pulses.

 

5. The generation of a square wave is possible in the mode

a) mode 1

b) mode 2

c) mode 3

d) mode 4

Answer: c

Explanation: When the count N loaded is even, then for half of the count, the output remains high and for the remaining half it remains low. If the count loaded is odd, the first clock pulse decrements it by 1 resulting in an even count value.

 

6. In control word register, if SC1=0 and SC0=1, then the counter selected is

a) counter 0

b) counter 1

c) counter 2

d) none

Answer: b

Explanation: SC denotes select counter.

 

7. In control word format, if RL1=1, RL0=1 then the operation performed is

a) read/load least significant byte only

b) read/load most significant byte only

c) read/load LSB first and then MSB

d) read/load MSB first and then LSB

Answer: c

Explanation: To access 16 bit, first LSB is loaded first, and then MSB.

 

8. If BCD=0, then the operation is

a) decimal count

b) hexadecimal count

c) binary count

d) octal count

Answer: b

Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.

 

9. The counter starts counting only if

a) GATE signal is low

b) GATE signal is high

c) CLK signal is low

d) CLK signal is high

Answer: b

Explanation: If the GATE signal is enabled, then the counter starts counting.

 

10. The control word register contents are used for

a) initializing the operating modes

b) selection of counters

c) choosing binary/BCD counters

d) all of the mentioned

Answer: d

Explanation: The control word register contents are used for

i) initializing the operating modes (mode 0-mode 4)

ii) selection of counters (counter0-counter2)

iii) choosing binary or BCD counters

iv) loading of the counter registers.

 

11. In direct memory access mode, the data transfer takes place

a) directly

b) indirectly

c) directly and indirectly

d) none of the mentioned

Answer: a

Explanation: In direct memory access mode, the data may transfer directly without the interference from the CPU.

 

12. In 8257 (DMA), each of the four channels has

a) a pair of two 8-bit registers

b) a pair of two 16-bit registers

c) one 16-bit register

d) one 8-bit register

Answer: b

Explanation: The DMA supports four channels, and each of the channels has a pair of two 16-bit registers, namely DMA address register and a terminal count register.

 

13. The common register(s) for all the four channels of 8257 is

a) DMA address register

b) Terminal count register

c) Mode set register and status register

d) None of the mentioned

Answer: c

Explanation: The two common registers for all the four channels of DMA are mode set register and status register.

 

14. In 8257 register format, the selected channel is disabled after the terminal count condition is reached when

a) Auto load is set

b) Auto load is reset

c) TC STOP bit is reset

d) TC STOP bit is set

Answer: d

Explanation: If the TC STOP bit is set, the selected channel is disabled after the terminal count condition is reached, and it further prevents any DMA cycle on the channel.

 

15. The IOR (active low) input line acts as output in

a) slave mode

b) master mode

c) master and slave mode

d) none of the mentioned

Answer: b

Explanation: The IOR (active low) is an active low bidirectional tristate input line, that acts as input in the slave mode, and acts as output in the master mode. In master mode, this signal is used to read data from a peripheral during a memory write cycle.

 

16. The IOW (active low) in its slave mode loads the contents of a data bus to

a) 8-bit mode register

b) upper/lower byte of 16-bit DMA address register

c) terminal count register

d) all of the mentioned

Answer: d

Explanation: In its slave mode, the IOW (active low) loads the contents of a data bus to 8-bit mode register, upper/lower byte of 16-bit DMA address register or terminal count register.

 

17. The pin that disables all the DMA channels by clearing the mode registers is

a) MARK

b) CLEAR

c) RESET

d) READY

Answer: c

Explanation: The RESET pin which is asynchronous input disables all the DMA channels by clearing the mode registers, and tristate all the control lines.

 

18. The pin that requests the access of the system bus is

a) HLDA

b) HRQ

c) ADSTB

d) None of the mentioned

Answer: b

Explanation: The hold request output requests the access of the system bus.

 

19. The pin that is used to write data to the addressed memory location, during DMA write operation is

a) MEMR (active low)

b) AEN

c) MEMW (active low)

d) IOW (active low)

Answer: c

Explanation: The MEMW (active low) is used to write data to the addressed memory location, during DMA write operation.

 

20. The pin that strobes the higher byte of the memory address, generated by the DMA controller into the latches is

a) AEN

b) ADSTB

c) TC

d) None of the mentioned

Answer: b

Explanation: The pin ADSTB strobes the higher byte of the memory address, generated by the DMA controller into the latches.

 

21. In the I/O mode, the 8255 ports work as

a) reset pins

b) set pins

c) programmable I/O ports

d) only output ports

Answer: c

Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.

 

22. In BSR mode, only port C can be used to

a) set individual ports

b) reset individual ports

c) set and reset individual ports

d) programmable I/O ports

Answer: c

Explanation: In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port bits.

 

23. The feature of mode 0 is

a) any port can be used as input or output

b) output ports are latched

c) maximum of 4 ports are available

d) all of the mentioned

Answer: d

Explanation: In mode 0, any port can be used as input or output and output ports are latched.

 

24. The strobed input/output mode is another name of

a) mode 0

b) mode 1

c) mode 2

d) none

Answer: b

Explanation: In this mode, the handshaking signals control the input or output action of the specified port.

 

25. If the value of the pin STB (Strobe Input) falls to low level, then

a) input port is loaded into input latches

b) input port is loaded into output latches

c) output port is loaded into input latches

d) output port is loaded into output latches

Answer: a

Explanation: If the value of the pin STB (Strobe Input) falls to low level, the input port is loaded into input latches.

 

26. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of

a) Control word register

b) CPU

c) Printer

d) Ports

Answer: c

Explanation: This signal indicates that the printer is selected.

 

27. The pulse width of the signal INIT at the receiving terminal must be more than

a) 10 microseconds

b) 20 microseconds

c) 40 microseconds

d) 50 microseconds

Answer: d

Explanation: The pulse width of the signal must be more than 50microseconds at the receiving terminal.

 

28. The level of the signal ERROR(active low) becomes ‘low’ when the printer is in

a) Paper end state

b) Offline state

c) Error state

d) All of the mentioned

Answer: d

Explanation: The level of the signal ERROR(active low) becomes ‘low’ when the printer is in the Paper end state, Offline state and Error state.

 

29. The signals that are provided to maintain proper data flow and synchronization between the data transmitter and receiver are

a) handshaking signals

b) control signals

c) input signals

d) none

Answer: a

Explanation: Handshaking signals maintain proper data flow and synchronization.

 

30. The feature of mode 2 of 8255 is

a) single 8-bit port is available

b) both inputs and outputs are latched

c) port C is used for generating handshake signals

d) all of the mentioned

Answer: d

Explanation: In mode 2 of 8255, a single 8-bit port is available i.e group A.

 

31. Programmable peripheral input-output port is another name for

a) serial input-output port

b) parallel input-output port

c) serial input port

d) parallel output port

Answer: b

Explanation: The parallel input-output port chip 8255 is also known as programmable peripheral input-output port.

 

32. Port C of 8255 can function independently as

a) input port

b) output port

c) either input or output ports

d) both input and output ports

Answer: c

Explanation: Port C can function independently either as input or as output ports.

 

33. All the functions of the ports of 8255 are achieved by programming the bits of an internal register called

a) data bus control

b) read logic control

c) control word register

d) none of the mentioned

Answer: c

Explanation: By programming the bits of control word register, the operations of the ports are specified.

 

34. The data bus buffer is controlled by

a) control word register

b) read/write control logic

c) data bus

d) none of the mentioned

Answer: b

Explanation: The data bus buffer is controlled by read/write control logic.

 

35. The input provided by the microprocessor to the read/write control logic is

a) RESET

b) A1

c) WR(ACTIVE LOW)

d) All of the mentioned

Answer: d

Explanation: RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs provided by the microprocessor to the read/write control logic of 8255.

 

36. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor is

a) control word register

b) read/write control logic

c) 3-state bidirectional buffer

d) none of the mentioned

Answer: c

Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the execution of input or output instructions by the microprocessor.

 

37. The port that is used for the generation of handshake lines in mode 1 or mode 2 is

a) port A

b) port B

c) port C Lower

d) port C Upper

Answer: d

Explanation: Port C upper is used for the generation of handshake lines in mode 1 or mode 2.

 

38. If A1=0, A0=1 then the input read cycle is performed from

a) port A to data bus

b) port B to data bus

c) port C to data bus

d) CWR to data bus

Answer: b

Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.

 

39. The function, ‘data bus tristated’ is performed when

a) CS(active low) = 1

b) CS(active low) = 0

c) CS(active low) = 0, RD(active low) = 1, WR(active low) = 1

d) CS(active low) = 1 OR CS(active low) = 0, RD(active low) = 1, WR(active low) = 1

Answer: d

Explanation: The data bus is tristated when chip select pin=1 or chip select pin=0 and read and write signals are high i.e 1.

 

40. The pin that clears the control word register of 8255 when enabled is

a) CLEAR

b) SET

c) RESET

d) CLK

Answer: c

Explanation: If reset pin is enabled then the control word register is cleared.