8086/8088 Architecture

1. The instruction that is used to transfer the data from source operand to destination operand is

a) data copy/transfer instruction

b) branch instruction

c) arithmetic/logical instruction

d) string instruction

Answer: a

Explanation: These instructions are used to copy and transfer the instructions.

 

2. Which of the following is not a data copy/transfer instruction?

a) MOV

b) PUSH

c) DAS

d) POP

Answer: c

Explanation: DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.

 

3. The instructions that involve various string manipulation operations are

a) branch instructions

b) flag manipulation instructions

c) shift and rotate instructions

d) string instructions

Answer: d

Explanation: The string instructions perform operations on strings such as load, move, scan, compare etc.

 

4. Which of the following instruction is not valid?

a) MOV AX, BX

b) MOV DS, 5000H

c) MOV AX, 5000H

d) PUSH AX

Answer: b

Explanation: Both the source and destination operands cannot be memory locations except for string instructions.

 

5. In PUSH instruction, after each execution of the instruction, the stack pointer is

a) incremented by 1

b) decremented by 1

c) incremented by 2

d) decremented by 2

Answer: d

Explanation: The actual current stack-top is always occupied by the previously pushed data. So, the push operation decrements SP by 2 and then stores the two bytes contents of the operand onto the stack.

 

6. The instruction that pushes the contents of the specified register/memory location on to the stack is

a) PUSHF

b) POPF

c) PUSH

d) POP

Answer: c

Explanation: Since PUSH operation transfers data to stack from a register or memory location.

 

7. In POP instruction, after each execution of the instruction, the stack pointer is

a) incremented by 1

b) decremented by 1

c) incremented by 2

d) decremented by 2

Answer: c

Explanation: The actual current stack top is poped into the specific operand as the contents of stack top memory is stored in AL&SP and further contents of the memory location pointed to by SP are copied to AH & SP.

 

8. The instructions that are used for reading an input port and writing an output port respectively are

a) MOV, XCHG

b) MOV, IN

c) IN, MOV

d) IN, OUT

Answer: d

Explanation: The address of the input/output port may be specified directly or indirectly.

Example for input port: IN AX, DX; This instruction reads data from a 16-bit port whose address is in DX and stores it in AX

Example for output port: OUT 03H, AL; This sends data available in AL to a port whose address is 03H.

 

9. The instruction that is used for finding out the codes in case of code conversion problems is

a) XCHG

b) XLAT

c) XOR

d) JCXZ

Answer: b

Explanation: The translate(XLAT) instruction is used to find codes.

 

10. The instruction that loads effective address formed by destination operand into the specified source register is

a) LEA

b) LDS

c) LES

d) LAHF

Answer: a

Explanation: The instruction, LEA loads effective address and is more useful for assembly language rather than for machine language.

 

11. The instruction that loads the AH register with the lower byte of the flag register is

a) SAHF

b) AH

c) LAHF

d) PUSHF

Answer: c

Explanation: The instruction LAHF(Load AH from a lower byte of Flag) may be used to observe the status of all the condition code flags(except overflow flag) at a time.

 

12. The instruction that pushes the flag register on to the stack is

a) PUSH

b) POP

c) PUSHF

d) POPF

Answer: c

Explanation: The instruction PUSHF(push flags to stack) pushes the flag register on to the stack.

 

13. The instruction that loads the flag register completely from the word contents of the memory location is

a) PUSH

b) POP

c) PUSHF

d) POPF

Answer: d

Explanation: POPF is pop flags to stack.

 

14. The instruction that adds immediate data/contents of the memory location specified in an instruction/register to the contents of another register/memory location is

a) SUB

b) ADD

c) MUL

d) DIV

Answer: b

Explanation: ADD instruction adds the data.

 

15. The instruction that supports addition when carry exists is

a) ADD

b) ADC

c) ADD & ADC

d) None of the mentioned

Answer: b

Explanation: ADC(Add with Carry) instruction performs the same operation as ADD operation, but adds the carry flag bit to the result.

 

16. If an interrupt is generated from outside the processor then it is an

a) internal interrupt

b) external interrupt

c) interrupt

d) none of the mentioned

Answer: b

Explanation: If an external device or a signal interrupts the processor from outside then it is an external interrupt.

 

17. If the interrupt is generated by the execution of an interrupt instruction then it is

a) internal interrupt

b) external interrupt

c) interrupt-in-interrupt

d) none of the mentioned

Answer: a

Explanation: The internal interrupt is generated internally by the processor circuit or by the execution of an interrupt instruction.

 

18. Example of an external interrupt is

a) divide by zero interrupt

b) keyboard interrupt

c) overflow interrupt

d) type2 interrupt

Answer: b

Explanation: Since the keyboard is external to the processor, it is an external interrupt.

 

19. Example of an internal interrupt is

a) divide by zero interrupt

b) overflow interrupt

c) interrupt due to INT

d) all of the mentioned

Answer: d

Explanation: Since the interrupts occur within the processor itself, they are called internal interrupts.

 

20. The interrupt request that is independent of IF flag is

a) NMI

b) TRAP

c) Divide by zero

d) All of the mentioned

Answer: d

Explanation: These requests are independent of IF flag.

 

21. The type of the interrupt may be passed to the interrupt structure of CPU from

a) interrupt service routine

b) stack

c) interrupt controller

d) none of the mentioned

Answer: c

Explanation: After an interrupt is acknowledged, the CPU computes the vector address from the type of the interrupt that may be passed to the internal structure of the CPU from an interrupt controller in case of external interrupts.

 

22. During the execution of an interrupt, the data pushed into the stack is the content of

a) IP

b) CS

c) PSW

d) All of the mentioned

Answer: d

Explanation: The contents of IP, CS and PSW are pushed into the stack during the execution.

 

23. After every response to the single step interrupt the flag that is cleared is

a) IF (Interrupt Flag)

b) TF (Trap Flag)

c) OF (Overflow Flag)

d) None of the mentioned

Answer: b

Explanation: If the trap flag is set then the processor enters the single step execution mode. After the execution, the trap flag is cleared.

 

24. At the end of ISR, the instruction should be

a) END

b) ENDS

c) IRET

d) INTR

Answer: c

Explanation: After the execution of the ISR, the control must go to the previous program (maybe main program) which was being executed. To execute it, IRET is placed at the end of ISR.

 

25. When the CPU executes IRET,

a) contents of IP and CS are retrieved

b) the control transfers from ISR to main program

c) clears the trap flag

d) clears the interrupt flag

Answer: a

Explanation: When the instruction IRET is executed, the contents of flags, IP and CS which were saved at the stack by the CALL instruction are retrieved to the respective registers.

 

26. The stack pointer register contains

a) address of the stack segment

b) pointer address of the stack segment

c) offset of address of stack segment

d) data present in the stack segment

Answer: c

Explanation: The stack pointer register contains the offset of the address of the stack segment.

 

27. The stack segment register contains

a) address of the stack segment

b) base address of the stack segment

c) pointer address of the stack segment

d) data in the stack segment

Answer: b

Explanation: The stack segment register contains base address of the stack segment in the memory. The stack pointer register (sP) and stack segment register (SS) together address the stack-top.

 

28. PUSH operation

a) decrements SP

b) increments SP

c) decrements SS

d) increments SS

Answer: a

Explanation: Each PUSH operation decrements the SP ( Stack Pointer) register.

 

29. POP operation

a) decrements SP

b) increments SP

c) decrements SS

d) increments SS

Answer: b

Explanation: Each POP operation increments the SP ( Stack Pointer) register.

 

30. The register or memory location that is pushed into the stack at the end must be

a) popped off last

b) pushed off first

c) popped off first

d) pushed off last

Answer: c

Explanation: The data can be retrieved by POP operation and as in stack, the data that is pushed at the end must be popped off first.

 

31. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK

the ASSUME directive directs to the assembler the

a) address of the stack segment

b) pointer address of the stack segment

c) name of the stack segment

d) name of the stack, code and data segments

Answer: d

Explanation: The directive ASSUME facilitates to name the segments with the desired name that is not a mnemonic or keyword.

 

32. When a stack segment is initialised then

a) SS and SP are initialised

b) only SS is initialised

c) only SP is initialised

d) SS and SP need not be initialised

Answer: a

Explanation: Though the Stack segment is initialised, the SS and SP pointers must be initialised.

 

33. The number of PUSH instructions and POP instructions in a subroutine must be

a) PUSH instructions must be greater than POP instructions

b) POP instructions must be greater than PUSH instructions

c) Both must be equal

d) Instructions may be any kind

Answer: c

Explanation: The number of PUSH instructions must be equal to the number of POP instructions.

 

34. 8086 does not support

a) Arithmetic operations

b) logical operations

c) BCD operations

d) Direct BCD packed multiplication

Answer: d

Explanation: The 8086 microprocessor does not support direct BCD packed operations.

 

35. For 8086 microprocessor, the stack segment may have a memory block of a maximum of

a) 32K bytes

b) 64K bytes

c) 16K bytes

d) NONE

Answer: b

Explanation: In 8086 microprocessor, the memory segments each have a memory of 64K bytes.

 

36. The bit that indicates whether the segment has been accessed by the CPU or not is

a) base address

b) attribute bit

c) present bit

d) granular bit

Answer: b

Explanation: The accessed bit or attribute bit (A) indicates whether the segment has been accessed by the CPU or not.

 

37. The TYPE field of a descriptor is used to find the

a) descriptor type

b) segment type

c) descriptor and segment type

d) none

Answer: c

Explanation: The type field decides the descriptor type and hence the segment type.

 

38. If the segment descriptor bit, S=0, then the descriptor is

a) data segment descriptor

b) code segment descriptor

c) system descriptor

d) all of the mentioned

Answer: c

Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.

 

39. The bit that indicates whether the segment is page addressable is

a) base address

b) attribute bit

c) present bit

d) granularity bit

Answer: d

Explanation: The granularity bit indicates whether the segment is page addressable.

 

40. If the Default operation size bit, D=1, the code segment operation size selected is

a) 8-bit

b) 16-bit

c) 32-bit

d) 64-bit

Answer: c

Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand segment.

 

41. The segment descriptor contains

a) access rights

b) limit

c) base address

d) all of the mentioned

Answer: d

Explanation: The segment descriptors are 8-byte quantities containing access right or attribute bits along with the base and limit of the segments.

 

42. Which of the following is not a type of segment descriptor?

a) system descriptors

b) local descriptors

c) gate descriptors

d) none

Answer: d

Explanation: The five types of segment descriptors of 80386 are:

Code or data segment descriptors

System descriptors

Local descriptors

TSS(task state segment) descriptors

Gate descriptors.

 

43. The limit field of the descriptor is of

a) 10 bits

b) 8 bits

c) 16 bits

d) 20 bits

Answer: d

Explanation: The limit field of the descriptor is of 20 bits.

 

44. The starting address of the segment in physical memory is decided by

a) physical memory

b) segment descriptors

c) operating system

d) base address

Answer: c

Explanation: The base address that marks the starting address of the segment in physical memory is decided by the operating system and is of 32 bits.

 

45. The total descriptors that the 80386 can handle is

a) 2K

b) 8K

c) 4K

d) 16K

Answer: d

Explanation: 80386 can handle total 16K descriptors and hence segments.