1. The DMA differs from the interrupt mode by __________
a) The involvement of the processor for the operation
b) The method of accessing the I/O devices
c) The amount of data transfer possible
d) None of the mentioned
Answer: d
Explanation: DMA is an approach of performing data transfers in bulk between memory and the external device without the intervention of the processor.
2. The DMA transfers are performed by a control circuit called as __________
a) Device interface
b) DMA controller
c) Data controller
d) Overlooker
Answer: b
Explanation: The Controller performs the functions that would normally be carried out by the processor.
3. In DMA transfers, the required signals and addresses are given by the __________
a) Processor
b) Device drivers
c) DMA controllers
d) The program itself
Answer: c
Explanation: The DMA controller acts as a processor for DMA transfers and overlooks the entire process.
4. After the completion of the DMA transfer, the processor is notified by __________
a) Acknowledge signal
b) Interrupt signal
c) WMFC signal
d) None of the mentioned
Answer: b
Explanation: The controller raises an interrupt signal to notify the processor that the transfer was complete.
5. The DMA controller has _______ registers.
a) 4
b) 2
c) 3
d) 1
Answer: c
Explanation: The Controller uses the registers to store the starting address, word count and the status of the operation.
6. When the R/W bit of the status register of the DMA controller is set to 1.
a) Read operation is performed
b) Write operation is performed
c) Read & Write operation is performed
d) None of the mentioned
Answer: a
Explanation: None.
7. The controller is connected to the ____
a) Processor BUS
b) System BUS
c) External BUS
d) None of the mentioned
Answer: b
Explanation: The controller is directly connected to the system BUS to provide faster transfer of data.
8. Can a single DMA controller perform operations on two different disks simultaneously?
a) True
b) False
Answer: a
Explanation: The DMA controller can perform operations on two different disks if the appropriate details are known.
9. The technique whereby the DMA controller steals the access cycles of the processor to operate is called __________
a) Fast conning
b) Memory Con
c) Cycle stealing
d) Memory stealing
Answer: c
Explanation: The controller takes over the processor’s access cycles and performs memory operations.
10. The technique where the controller is given complete access to main memory is __________
a) Cycle stealing
b) Memory stealing
c) Memory Con
d) Burst mode
Answer: d
Explanation: The controller is given full control of the memory access cycles and can transfer blocks at a faster rate.
11. The controller uses _____ to help with the transfers when handling network interfaces.
a) Input Buffer storage
b) Signal enhancers
c) Bridge circuits
d) All of the mentioned
Answer: a
Explanation: The controller stores the data to transfer in the buffer and then transfers it.
12. To overcome the conflict over the possession of the BUS we use ______
a) Optimizers
b) BUS arbitrators
c) Multiple BUS structure
d) None of the mentioned
Answer: b
Explanation: The BUS arbitrator is used to overcome the contention over the BUS possession.
13. The registers of the controller are ______
a) 64 bits
b) 24 bits
c) 32 bits
d) 16 bits
Answer: c
Explanation: None.
14. When the process requests for a DMA transfer?
a) Then the process is temporarily suspended
b) The process continues execution
c) Another process gets executed
d) process is temporarily suspended & Another process gets executed
Answer: d
Explanation: The process requesting the transfer is paused and the operation is performed, meanwhile another process is run on the processor.
15. The DMA transfer is initiated by _____
a) Processor
b) The process being executed
c) I/O devices
d) OS
Answer: c
Explanation: The transfer can only be initiated by an instruction of a program being executed.
16. In memory-mapped I/O ____________
a) The I/O devices and the memory share the same address space
b) The I/O devices have a separate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation
Answer: a
Explanation: Its the different modes of accessing the i/o devices.
17. The usual BUS structure used to connect the I/O devices is ___________
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
Answer: c
Explanation: BUS is a collection of address, control and data lines used to connect the various devices of the computer.
18. In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.
a) False
b) True
Answer: b
Explanation: This type of access is called as I/O mapped devices.
19. The advantage of I/O mapped devices to memory mapped is ___________
a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a bigger buffer space
c) The devices have to deal with fewer address lines
d) No advantage as such
Answer: c
Explanation: Since the I/O mapped devices have a separate address space the address lines are limited by the amount of the space allocated.
20. The system is notified of a read or write operation by ___________
a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) Sending a special signal along the BUS
Answer: d
Explanation: It is necessary for the processor to send a signal intimating the request as either read or write.
21. To overcome the lag in the operating speeds of the I/O device and the processor we use ___________
a) BUffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
Answer: b
Explanation: The processor operating is much faster than that of the I/O devices, so by using the status flags the processor need not wait till the I/O operation is done. It can continue with its work until the status flag is set.
22.The method of accessing the I/O devices by repeatedly checking the status flags is ___________
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None of the mentioned
Answer: a
Explanation: In this method, the processor constantly checks the status flags, and when it finds that the flag is set it performs the appropriate operation.
23. The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is?
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
Answer: c
Explanation: This is a method of accessing the I/O devices which gives the complete power to the devices, enabling them to intimate the processor when they’re ready for transfer.
24. The method which offers higher speeds of I/O transfers is ___________
a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA
Answer: d
Explanation: In DMA the I/O devices are directly allowed to interact with the memory without the intervention of the processor and the transfers take place in the form of blocks increasing the speed of operation.
25. The process wherein the processor constantly checks the status flags is called as ___________
a) Polling
b) Inspection
c) Reviewing
d) Echoing
Answer: a
Explanation: None.
26. The interrupt-request line is a part of the ___________
a) Data line
b) Control line
c) Address line
d) None of the mentioned
Answer: b
Explanation: The Interrupt-request line is a control line along which the device is allowed to send the interrupt signal.
27. The return address from the interrupt-service routine is stored on the ___________
a) System heap
b) Processor register
c) Processor stack
d) Memory
Answer: c
Explanation: The Processor after servicing the interrupts as to load the address of the previous process and this address is stored in the stack.
28. The signal sent to the device from the processor to the device after receiving an interrupt is ___________
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal
Answer: a
Explanation: The Processor upon receiving the interrupt should let the device know that its request is received.
29.When the process is returned after an interrupt service ______ should be loaded again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
a) i, iv
b) ii, iii and iv
c) iii, iv
d) i, ii
Answer: d
Explanation: None.
30. The time between the receiver of an interrupt and its service is ______
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time
Answer: b
Explanation: The delay in servicing of an interrupt happens due to the time is taken for contact switch to take place.
31. Interrupts form an important part of _____ systems.
a) Batch processing
b) Multitasking
c) Real-time processing
d) Multi-user
Answer: c
Explanation: This forms an important part of the Real time system since if a process arrives with greater priority then it raises an interrupt and the other process is stopped and the interrupt will be serviced.
32. A single Interrupt line can be used to service n different devices.
a) True
b) False
Answer: a
Explanation: None.
33. ______ type circuits are generally used for interrupt service lines.
i) open-collector
ii) open-drain
iii) XOR
iv) XNOR
a) i, ii
b) ii
c) ii, iii
d) ii, iv
Answer: a
Explanation: None.
34.The resistor which is attached to the service line is called _____
a) Push-down resistor
b) Pull-up resistor
c) Break down resistor
d) Line resistor
Answer: b
Explanation: This resistor is used to pull up the voltage of the interrupt service line.
35. An interrupt that can be temporarily ignored is ___________
a) Vectored interrupt
b) Non-maskable interrupt
c) Maskable interrupt
d) High priority interrupt
Answer: c
Explanation: The maskable interrupts are usually low priority interrupts which can be ignored if a higher priority process is being executed.
36. The 8085 microprocessor responds to the presence of an interrupt ___________
a) As soon as the trap pin becomes ‘LOW’
b) By checking the trap pin for ‘high’ status at the end of each instruction fetch
c) By checking the trap pin for ‘high’ status at the end of execution of each instruction
d) By checking the trap pin for ‘high’ status at regular intervals
Answer: c
Explanation: The 8085 microprocessor are designed to complete the execution of the current instruction and then to service the interrupts.
37. CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged.
a) A hardware interrupt is needed
b) A software interrupt is needed
c) Either hardware or software interrupt is needed
d) A non-privileged instruction (which does not generate an interrupt)is needed
Answer: b
Explanation: A software interrupt by some program which needs some CPU service, at that time the two modes can be interchanged.
38. Which interrupt is unmaskable?
a) RST 5.5
b) RST 7.5
c) TRAP
d) Both RST 5.5 and 7.5
Answer: c
Explanation: The trap is a non-maskable interrupt as it deals with the ongoing process in the processor. The trap is initiated by the process being executed due to lack of data required for its completion. Hence trap is unmaskable.
39. From amongst the following given scenarios determine the right one to justify interrupt mode of data transfer.
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
a) i and ii
b) ii
c) i, ii and iv
d) iv
Answer: d
Explanation: None.
40.How can the processor ignore other interrupts when it is servicing one ___________
a) By turning off the interrupt request line
b) By disabling the devices from sending the interrupts
c) BY using edge-triggered request lines
d) All of the mentioned
Answer: d
Explanation: None.
41. When dealing with multiple devices interrupts, which mechanism is easy to implement?
a) Polling method
b) Vectored interrupts
c) Interrupt nesting
d) None of the mentioned
Answer: a
Explanation: In this method, the processor checks the IRQ bits of all the devices, whichever is enabled first that device is serviced.
42. The interrupt servicing mechanism in which the requesting device identifies itself to the processor to be serviced is ___________
a) Polling
b) Vectored interrupts
c) Interrupt nesting
d) Simultaneous requesting
Answer: b
Explanation: None.
43. In vectored interrupts, how does the device identify itself to the processor?
a) By sending its device id
b) By sending the machine code for the interrupt service routine
c) By sending the starting address of the service routine
d) None of the mentioned
Answer: c
Explanation: By sending the starting address of the routine the device ids the routine required and thereby identifying itself.
44. The code sent by the device in vectored interrupt is _____ long.
a) upto 16 bits
b) upto 32 bits
c) upto 24 bits
d) 4-8 bits
Answer: d
Explanation: None.
45. The starting address sent by the device in vectored interrupt is called as __________
a) Location id
b) Interrupt vector
c) Service location
d) Service id
Answer: b
Explanation: None.
46. The processor indicates to the devices that it is ready to receive interrupts ________
a) By enabling the interrupt request line
b) By enabling the IRQ bits
c) By activating the interrupt acknowledge line
d) None of the mentioned
Answer: c
Explanation: When the processor activates the acknowledge line the devices send their interrupts to the processor.
47. We describe a protocol of input device communication below:
i) Each device has a distinct address.
ii) The BUS controller scans each device in a sequence of increasing address value to determine if the entity wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the following.
a) Programmed mode of data transfer
b) DMA
c) Interrupt mode
d) Polling
Answer: d
Explanation: In polling, the processor checks each of the devices if they wish to perform data transfer and if they do it performs the particular operation.
48. Which one of the following is true with regard to a CPU having a single interrupt request line and single interrupt grant line?
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not possible.
iv) Both vectored and multiple interrupting devices are possible.
a) iii
b) i, iv
c) ii, iii
d) iii, iv
Answer: a
Explanation: None.
49. Which table handle stores the addresses of the interrupt handling sub-routines?
a) Interrupt-vector table
b) Vector table
c) Symbol link table
d) None of the mentioned
Answer: a
Explanation: None.
50. _________ method is used to establish priority by serially connecting all devices that request an interrupt.
a) Vectored-interrupting
b) Daisy chain
c) Priority
d) Polling
Answer: b
Explanation: In the Daisy chain mechanism, all the devices are connected using a single request line and they’re serviced based on the interrupting device’s priority.
51. In daisy chaining device 0 will pass the signal only if it has _______
a) Interrupt request
b) No interrupt request
c) Both No interrupt and Interrupt request
d) None of the mentioned
Answer: b
Explanation: In daisy chaining since there is only one request line and only one acknowledges line, the acknowledge signal passes from device to device until the one with the interrupt is found.
52. ______ interrupt method uses register whose bits are set separately by interrupt signal for each device.
a) Parallel priority interrupt
b) Serial priority interrupt
c) Daisy chaining
d) None of the mentioned
Answer: a
Explanation: None.
53. ______________ register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt.
a) Mass
b) Mark
c) Make
d) Mask
Answer: d
Explanation: None.
54. The added output of the bits of the interrupt register and the mask register is set as an input of ______________
a) Priority decoder
b) Priority encoder
c) Process id encoder
d) Multiplexer
Answer: b
Explanation: In a parallel priority system, the priority of the device is obtained by adding the contents of the interrupt register and the mask register.
55. Interrupts initiated by an instruction is called as _______
a) Internal
b) External
c) Hardware
d) Software
Answer: b
Explanation: None.
56. Input or output devices that are connected to computer are called ______________.
A. Input/Output Subsystem
B. Peripheral Devices
C. Interfaces
D. Interrupt
Ans : B
Explanation: Input or output devices that are connected to computer are called peripheral devices.
57. How many types of modes of I/O Data Transfer?
A. 2
B. 3
C. 4
D. 5
Ans : B
Explanation: Generally three types of modes which are : Programmed I/O, Interrupt Initiated I/O, Direct Memory Access
58. Keyboard and Mouse Comes under?
A. Input peripherals
B. Output peripherals
C. Input-Output peripherals
D. None of the above
Ans : A
Explanation: Allows user input, from the outside world to the computer. Example: Keyboard, Mouse etc.
59.The method which offers higher speeds of I/O transfers is ___________
A. Interrupts
B. Memory mapping
C. Program-controlled I/O
D. DMA
Ans : D
Explanation: In DMA the I/O devices are directly allowed to interact with the memory without the intervention of the processor and the transfers take place in the form of blocks increasing the speed of operation.
60. In memory-mapped I/O ____________
A. The I/O devices have a separate address space
B. The I/O devices and the memory share the same address space
C. A part of the memory is specifically set aside for the I/O operation
D. The memory and I/O devices have an associated address space
Ans : B
Explanation: Its the different modes of accessing the i/o devices.
61. The ________ circuit is basically used to extend the processor BUS to connect devices.
A. Router
B. Router
C. Bridge
D. None of the above
Ans : C
Explanation: The bridge circuit is basically used to extend the processor BUS to connect devices.
62. The ISA is an architectural standard developed by ______.
A. IBM
B. AT&T Labs
C. Microsoft
D. Oracle
Ans : A
Explanation: Industry Standard Architecture is an architectural standard developed by IBM for its PC’s.
63. The SCSI BUS is used to connect the video devices to a processor by providing a ______________.
A. Single Bus
B. USB
C. SCSI
D. parallel BUS.
Ans : D
Explanation: The SCSI BUS is used to connect the video devices to a processor by providing a parallel BUS.
64.Which of the following is true about DMA?
A. DMA is an approach of performing data transfers in bulk between memory and the external device without the intervention of the processor.
B. The DMA controller acts as a processor for DMA transfers and overlooks the entire process.
C. The DMA controller has 3 registers.
D. All of the above
Ans : D
Explanation: all of the above statement is true regarding DMA.
65. The registers of the controller are ______
A. 16 bit
B. 32 bit
C. 64 bit
D. 128 bit
Ans : B
Explanation: The registers of the controller are 32 bit.
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