1. Any signed negative binary number is recognised by its ________
a) MSB
b) LSB
c) Byte
d) Nibble
Answer: a
Explanation: Any negative number is recognized by its MSB (Most Significant Bit).
If it’s 1, then Ãt’s negative, else if it’s 0, then positive.
2. The parameter through which 16 distinct values can be represented is known as ________
a) Bit
b) Byte
c) Word
d) Nibble
Answer: c
Explanation: It can be represented up to 16 different values with the help of a Word. Nibble is a combination of four bits and Byte is a combination of 8 bits. It is “word” that is said to be a collection of 16-bits on most of the systems.
3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the number continuously by 2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
Answer: b
Explanation: On multiplying the decimal number continuously by 2, the binary equivalent is obtained by the collection of the integer part. However, if it’s an integer, then it’s binary equivalent is determined by dividing the number by 2 and collecting the remainders.
4. The representation of octal number (532.2)8 in decimal is ________
a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
Answer: a
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
(532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10
5. The decimal equivalent of the binary number (1011.011)2 is ________
a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
Answer: a
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along with the value at that index position.
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10
6. An important drawback of binary system is ________
a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number
Answer: a
Explanation: The most vital drawback of binary system is that it requires very large string of 1’s and 0’s to represent a decimal number. Hence, Hexadecimal systems are used by processors for calculation purposes as it compresses the long binary strings into small parts.
7. The decimal equivalent of the octal number (645)8 is ______
a) (450)10
b) (451)10
c) (421)10
d) (501)10
Answer: c
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
The decimal equivalent of the octal number (645)8 is 6 * 82 + 4 * 81 + 5 * 80 = 6 * 64 + 4 * 8 + 5 = 384 + 32 + 5 = (421)10.
8. The largest two digit hexadecimal number is ________
a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
Answer: c
Explanation: (FE)16 is 254 in decimal system, while (FD)16 is 253. (EF)16 is 239 in decimal system. And, (FF)16 is 255. Thus, The largest two-digit hexadecimal number is (FF)16.
9. Representation of hexadecimal number (6DE)H in decimal:
a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
Answer: a
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base index along with the value at that index position.
In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.
10. The quantity of double word is ________
a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
Answer: b
Explanation: One word means 16 bits, Thus, the quantity of double word is 32 bits.
Sanfoundry Global Education & Learning Series – Digital Circuits.
11. 1’s complement of 1011101 is ____________
a) 0101110
b) 1001101
c) 0100010
d) 1100101
Answer: c
Explanation: 1’s complement of a binary number is obtained by reversing the binary bits. All the 1’s to 0’s and 0’s to 1’s.
12. 2’s complement of 11001011 is ____________
a) 01010111
b) 11010100
c) 00110101
d) 11100010
Answer: c
Explanation: 2’s complement of a binary number is obtained by finding the 1’s complement of the number and then adding 1 to it.
2’s complement of 11001011 = 00110100 + 1 = 00110101.
13. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________
a) 01001
b) 11010
c) 10101
d) 10100
Answer: d
Explanation: Steps For Subtraction using 1’s complement are:
-> 1’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and 1 is added to the last bit of the result.
-> Else, if there is no carry, then 1’s complement of the result is found out and a ‘-’ sign preceeds the result.
14. On subtracting (010110)2 from (1011001)2 using 2’s complement, we get ____________
a) 0111001
b) 1100101
c) 0110110
d) 1000011
Answer: d
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.
15. On subtracting (001100)2 from (101001)2 using 2’s complement, we get ____________
a) 1101100
b) 011101
c) 11010101
d) 11010111
Answer: b
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.
16. On addition of 28 and 18 using 2’s complement, we get ____________
a) 00101110
b) 0101110
c) 00101111
d) 1001111
Answer: b
Explanation: Steps for Binary Addition Using 2’s complement:
-> The binary equivalent of the two numbers are obtained and added using the rules of binary addition.
17. On addition of +38 and -20 using 2’s complement, we get ____________
a) 11110001
b) 100001110
c) 010010
d) 110101011
Answer: c
Explanation: Steps for Binary Addition Using 2’s complement:
-> The 2’s complement of the addend is found out and added to the first number.
-> The result is the 2’s complement of the sum obtained.
18. On addition of -46 and +28 using 2’s complement, we get ____________
a) -10010
b) -00101
c) 01011
d) 0100101
Answer: a
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary addition is performed.
Augend is 28 and Subtrahend is -46.
19. On addition of -33 and -40 using 2’s complement, we get ____________
a) 1001110
b) -110101
c) 0110001
d) -1001001
Answer: d
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary addition is performed.
Augend is -40 and Subtrahend is -33.
20. On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1
Answer: d
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.
21. 1’s complement of 1011101 is ____________
a) 0101110
b) 1001101
c) 0100010
d) 1100101
Answer: c
Explanation: 1’s complement of a binary number is obtained by reversing the binary bits. All the 1’s to 0’s and 0’s to 1’s.
22. 2’s complement of 11001011 is ____________
a) 01010111
b) 11010100
c) 00110101
d) 11100010
Answer: c
Explanation: 2’s complement of a binary number is obtained by finding the 1’s complement of the number and then adding 1 to it.
2’s complement of 11001011 = 00110100 + 1 = 00110101.
23. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________
a) 01001
b) 11010
c) 10101
d) 10100
Answer: d
Explanation: Steps For Subtraction using 1’s complement are:
-> 1’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and 1 is added to the last bit of the result.
-> Else, if there is no carry, then 1’s complement of the result is found out and a ‘-’ sign preceeds the result.
24. On subtracting (010110)2 from (1011001)2 using 2’s complement, we get ____________
a) 0111001
b) 1100101
c) 0110110
d) 1000011
Answer: d
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.
25. On subtracting (001100)2 from (101001)2 using 2’s complement, we get ____________
a) 1101100
b) 011101
c) 11010101
d) 11010111
Answer: b
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.
26. On addition of 28 and 18 using 2’s complement, we get ____________
a) 00101110
b) 0101110
c) 00101111
d) 1001111
Answer: b
Explanation: Steps for Binary Addition Using 2’s complement:
-> The binary equivalent of the two numbers are obtained and added using the rules of binary addition.
27. On addition of +38 and -20 using 2’s complement, we get ____________
a) 11110001
b) 100001110
c) 010010
d) 110101011
Answer: c
Explanation: Steps for Binary Addition Using 2’s complement:
-> The 2’s complement of the addend is found out and added to the first number.
-> The result is the 2’s complement of the sum obtained.
28. On addition of -46 and +28 using 2’s complement, we get ____________
a) -10010
b) -00101
c) 01011
d) 0100101
Answer: a
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary addition is performed.
Augend is 28 and Subtrahend is -46.
29. On addition of -33 and -40 using 2’s complement, we get ____________
a) 1001110
b) -110101
c) 0110001
d) -1001001
Answer: d
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary addition is performed.
Augend is -40 and Subtrahend is -33.
30. On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1
Answer: d
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.
31. Which of the following is not a positional number system?
a) Roman Number System
b) Octal Number System
c) Binary Number System
d) Hexadecimal Number System
Answer: a
Explanation: The Roman number system isn’t a positional number system since it uses symbols to represent numbers.
The octal number system uses digits from 0-7, the binary number system uses digits from 0-1 whereas, the hexadecimal number system uses digits from 0-15.
32. The value of radix in binary number system is _____________
a) 2
b) 8
c) 10
d) 1
Answer: a
Explanation: In a binary number system, the value of base or radix is 2. The binary system uses only two digits for the representation of numbers, therefore its base id has chosen to be 2.
33. The binary equivalent of the decimal number 10 is __________
a) 0010
b) 10
c) 1010
d) 010
Answer: c
Explanation: To get the binary equivalent of any number, we need to divide the number by 2 and obtain the remainders as :We then write the remainders in the reverse order as 1010 .
34. A computer language that is written in binary codes only is _____
a) machine language
b) C
c) C#
d) pascal
Answer: a
Explanation: Machine Language is written in binary codes only. It can be easily understood by the computer and is very difficult for us to understand. A machine language, unlike other languages, requires no translators or interpreters.
35. The octal equivalent of 1100101.001010 is ______
a) 624.12
b) 145.12
c) 154.12
d) 145.21
Answer: b
Explanation: The octal equivalent is obtained by grouping the numbers into three, from right to left before decimal and from right to left after the decimal place.
Here, i.e. 145.12 is the octal equivalent of the number.
36. The input hexadecimal representation of 1110 is _______________
a) 0111
b) E
c) 15
d) 14
Answer: b
Explanation: In hexadecimal number system, 1110 = 15, which is represented by the alphabet E.
Some representations are:
A 10
B 11
C 12
D 13
E 14
F 15.
37. A bit in a computer terminology means either 0 or 1.
a) True
b) False
Answer: a
Explanation: A bit stands for a binary digit. A binary digit can have only two digits i.e. 0 or 1. A binary number consisting of n-bits is called an n-bit number.
38. Convert the binary equivalent 10101 to its decimal equivalent.
a) 21
b) 12
c) 22
d) 31
Answer: a
Explanation: To convert a binary number to its decimal equivalent follow these steps :
24 * 1 + 23 * 0 + 22 *1 + 21 * 0 + 20 * 1 = 21.
Therefore, the answer is 21.
39. Which of the following is not a binary number?
a) 1111
b) 101
c) 11E
d) 000
Answer: c
Explanation: A binary number can have only two possible digits, 0 and 1. In the third option, there is an alphabet E present which makes it an invalid binary number. Alphabets are only allowed in the hexadecimal number system.
40. Which of the following is the correct representation of a binary number?
a) (124)2
b) 1110
c) (110)2
d) (000)2
Answer: d
Explanation: The binary numbers should comprise only two digits 0 and 1.
Also, for the base, the value should be 2 and it should be written as a subscript enclosing the entire number. Here, the fourth option gives the correct representation.
41. What could be the maximum value of a single digit in an octal number system?
a) 8
b) 7
c) 6
d) 5
Answer: b
Explanation: The maximum value in any number system is one less than the value of the base. The base in an octal number system is 8, therefore, the maximum value of the single digit is 7. It takes digits from 0 to 7.
42. In a number system, each position of a digit represents a specific power of the base.
a) True
b) False
Answer: a
Explanation: In a number system, every digit is denoted by a specific power of base. Like in an octal system, consider the number 113, it will be represented as :
82 * 1 + 81 * 1 + 80 *3.
43. The maximum number of bits sufficient to represent an octal number in binary is _______
a) 4
b) 3
c) 7
d) 8
Answer: b
Explanation: The octal number system comprises of only 8 digits. Hence, three bits (23 = 8) are sufficient to represent any octal number in the binary format.
44. The binary number 111 in octal format is ________________
a) 6
b) 7
c) 8
d) 5
Answer: b
Explanation: Certain binary to octal representations are :
000=0
001=1
010=2
011=3
100=4
101=5
110=6
111=7.
45. Convert (22)8 into its corresponding decimal number.
a) 28
b) 18
c) 81
d) 82
Answer: b
Explanation: To convert an octal number to decimal number:
81 * 2 + 80 * 2 = 16 + 2 = 18.
Hence, the decimal equivalent is 18.
46. The octal equivalent of the binary number (0010010100)2 is ______________
a) 422
b) 242
c) 224
d) 226
Answer: c
Explanation: To obtain the octal equivalent, we take numbers in groups of 3, from right to left
47. Octal subtraction of (232)8 from (417)8 will give ______________
a) 165
b) 185
c) 815
d) 516
Answer: a
Explanation: Octal subtraction is done as follows:
417
– 232
________
165
The octal subtraction is the same as that of any other number system. The only difference is, like in a decimal number system, we borrow a group of 10, in a binary system we borrow a group of 2, in an octal number system, we borrow in groups of 8.
48. The 1’s complement of 0.101 is _________________
a) 1.010
b) 0.010
c) 0.101
d) 1.101
Answer: a
Explanation: The 1’s complement of a number is obtained by reversing the bits with value 1 to 0 and the bits with value 0 to 1.
Here, 0.101 gets converted to 1.010 in its 1’s complement format.
49. Convert (5401)8 to hexadecimal.
a) A01
b) A02
c) B01
d) C01
Answer: c
Explanation: To convert octal to hexadecimal, we first write binary format of the number and then make groups of 4 bits from right to left. Therefore, the hexadecimal equivalent is (B01)16.
50. Express the decimal format of the signed binary number (10010)2 .
a) 2
b) 12
c) -12
d) -2
Answer: d
Explanation: The first bit is the sign bit whereas the rest of the bits are magnitude bits. So the number is: 0010 = 21 * 1 =2
But, the sign bit is 1, Therefore the answer is : (-2)10.
51. What does the symbol D represent in a hexadecimal number system?
a) 8
b) 16
c) 13
d) 14
Answer: c
Explanation: The symbols A, B, C, D, E and F represent 10, 11, 12, 13, 14 and 15 respectively in a hexadecimal system. This system comprises of 15 numbers in total: digits from 0-9 and symbols from A to F.
52. ABC is a valid hexadecimal number.
a) True
b) False
Answer: a
Explanation: In a hexadecimal number system, alphabets are used for the representation of numbers from 10 to 15. Here, A represents 10, B represents 11 and C represents 12. Therefore, it is a valid hexadecimal number.
53. The maximum number of bits sufficient to represent a hexadecimal number in binary:
a) 4
b) 3
c) 7
d) 8
Answer: a
Explanation: The hexadecimal number system comprises of only 15 symbols: 10 digits and 5 symbols. Hence, three bits (24 = 16) are sufficient to represent any hexadecimal number in the binary format.
54. The binary number 1110 in hexadecimal format is _____________
a) 6
b) E
c) 14
d) 15
Answer: b
Explanation: Certain binary to hexadecimal representations are :
1010=A
1011=B
1100=C
1101=D
1110=E
1111=F.
55. Convert (52)16 into its decimal equivalent.
a) 28
b) 83
c) 80
d) 82
Answer: d
Explanation: To convert a hexadecimal number to decimal number:
161 * 5 + 160 * 2 = 80 + 2 = 82
Hence, the decimal equivalent is 82.
56. The hexadecimal equivalent of the binary number (0010010100)2 is :
a) (0B4)16
b) (0A4)16
c) 224
d) 0114
Answer: a
Explanation: To obtain the octal equivalent, we take numbers in groups of 3, from right to left as :
57. Hexadecimal Addition of (3A5)16 and (1B2)16 will give :
a) 557
b) 185
c) 815
d) 516
Answer: a
Explanation: Octal subtraction is done as follows:
3A5
+ 1B2
________
557
In hexadecimal addition of alphabets, we add the corresponding numbers they represent and then subtract the result from 16, then generate a carry of 1 to the next set of numbers.
Here, 5+2=7
A+B=10+11=21-16=5
3+1+1(carry)=5.
58. The 2’s complement of 10.11 :
a) 10
b) 0.010
c) 01.01
d) 10.01
Answer: a
Explanation: The 1’s complement of a number is obtained by reversing the bits with value 1 to 0 and the bits with value 0 to 1. Here, 10.11 gets converted to 01.00 in its 1’s complement format. Further, to convert 1’s complement into 2’s, we add 1 to the result. Here, 01.00+1=10.00.
59. Convert (6532)8 to hexadecimal.
a) (A01)16
b) (A02)16
c) (D5A)16
d) (C01)16
Answer: c
Explanation: To convert octal to hexadecimal, we first write binary format of the number and then make groups of 4 bits from right to left. Therefore, the hexadecimal equivalent is (D5A)16.
60. What do we call the point(decimal) in any hexadecimal number of the form 111.A3?
a) radix
b) hexadecimal point
c) decimal
d) octal point
Answer: b
Explanation: The decimal is often referred to as the hexadecimal point in hexadecimal representation of numbers.
It is referred to as the octal point in octal numbers.
61. A group of bits used to represent a symbol is called a ____________
a) byte
b) memory
c) nibble
d) code
Answer: a
Explanation: In binary coding, every symbol that appears in data is represented by a group of bits, which are called bytes. Computer codes use binary coding schemes.
62. BCD uses 6 bits to represent a symbol.
a) True
b) False
Answer: a
Explanation: In a Binary Coded Decimal format, 64 characters i.e. 26 different characters can be represented. It is one of the early computer codes.
63. Which of the following is not a type of computer code?
a) EBCDIC
b) BCD
c) ASCII
d) EDIC
Answer: d
Explanation: There is no coding scheme like EDIC. EBCDIC stands for Extended Binary Coded Decimal Interchange Code. BCD stands for Binary Coded Decimal. ASCII stands for American Standard Code for information interchange.
64. The BCD representation of (34)10 is _______________
a) 6
b) 7
c) 8
d) 5
Answer: b
Explanation: BCD numbers are represented as:
34 = (0011 0100)BCD.
Each digit is individually taken and an equivalent standard 4 bit term is written for the respective digit.
65. Perform BCD addition of (23)BCD + (20)BCD .
a) 00110100
b) 01000011
c) 10011
d) 11100
Answer: b
Explanation: To add any two BCD numbers :
Simply perform the addition : 23+20=43.
Then, write the equivalent BCD number = (0100 0011)BCD.
66. The weights used in Binary coded decimal code are:
a) 4,2,1
b) 8,4,2,1
c) 6,4,2,1
d) 2,1
Answer: b
Explanation: BCD is a weighted code and it uses the weights 8,4,2,1 respectively. It is often called the 8421 code. Since, it uses 4 bits for the representation therefore the weights are assigned as : 23 = 8, 22 = 4, 21 = 2, 20 = 1.
67. Write the decimal equivalent for (110001)BCD.
a) 31
b) 13
c) C1
d) 1C
Answer: a
Explanation: To obtain the decimal equivalent :
We start from the rightmost bit and make groups of 4, then write the decimal equivalent accordingly.
0011 0001 = (31)10.
68. The 9’s complement of 45 is _____________
a) 45
b) 54
c) 64
d) 46
Answer: b
Explanation: The 9’s complement of a number is obtained by subtracting each digit from 9. Here, 99-45=54. Therefore, the 9’s complement is 54.
69. The 10’s complement of 455 is _________
a) 543
b) 544
c) 545
d) 546
Answer: c
Explanation: To obtain the 10’s complement, we first obtain the 9’s complement and then add 1 to it.
999-455=544 (9’s)
544+1=545(10’s).
70. The Excess-3 representation of (0100)BCD is __________
a) 0110
b) 1110
c) 0111
d) 1100
Answer: c
Explanation: The excess-3 code is obtained by adding 3 to the BCD code.
Here, 0100+0011=0111.
Also, 4+3=7.
71. What does ASCII stand for?
a) American Standard Code for Information Interchange
b) American Scientific Code for Information Interchange
c) American Scientific Code for Interchanging Information
d) American Standard Code for Interchanging Information
Answer: a
Explanation: The ASCII codes are used to represent the bits into symbols and vice versa. ASCII is the American Standard Code which is used to exchange information.
72. The decimal representation for the character ‘!’ in ASCII is ____________
a) 31
b) 32
c) 33
d) 34
Answer: c
Explanation: The decimal representation of a few basic characters are:
33 : !
34 : ”
35: #
36 :$.
73. The two types of ASCII are _____________ and ____________
a) ASCII-4 and ASCII-8
b) ASCII-8 and ASCII-16
c) ASCII-7 and ASCII-8
d) ASCII-4 and ASCII-16
Answer: c
Explanation: The two types of ASCII are ASCII-7 and ASCII-8. ASCII-7 uses 7 bits for the representation of numbers and ASCII-8 uses 8-bits.
74. Any set of digits or alphabets are generally referred as ______________
a) Characters
b) Symbols
c) Bits
d) Bytes
Answer: a
Explanation: We refer to the digits and alphabets generally as characters. A character is generally a unit of information in computers.
75. The first 128 characters are the same in both the types of ASCII i.e. ASCII-7 and ASCII-8.
a) True
b) False
Answer: a
Explanation: There are two types of ASCII codes: ASCII-7 and ASCII-8. ASCII-7 uses 7 bits to represent a number whereas ASCII-8 uses 8-bits to represent a number.
76. The number of characters that can be represented in ASCII-8 are ______________
a) 128
b) 256
c) 32
d) 64
Answer: b
Explanation: ASCII-8 can represent 256 different characters. ASCII-8 uses 8-bits for the representation of numbers i.e. it can represent 28 = 256 different characters.
77. The zone of alphabetic characters from A to O in ASCII is _____________
a) 1000
b) 0100
c) 0010
d) 0001
Answer: b
Explanation: The zone used by ASCII for alphabets is 0100. For e.g. A is represented as 0100(zone)0001(digit). The hex equivalent is 41 for A. The zone used by numbers is 0011.
78. The representation of the number 8 in binary in ASCII-8 format _________
a) 00111000
b) 01001000
c) 1000
d) 00011000
Answer: a
Explanation: The ASCII-8 format will have 8 bits. The zone for the character 8 is 0011 and the digit is 1000. Therefore, its representation is 00111000.
79. Binary Coding for the letter X is ______________
a) 01011000
b) 00111000
c) 10001000
d) 00010100
Answer: a
Explanation: The binary coding for the letter X is 01011000. Here, 0101 is the zone whereas 1000 is the digit. The alphabets from P to Z have the zone 0101.
80. Express the ASCII equivalent of the signed binary number (00110010)2.
a) 2
b) 1
c) A
d) ,
Answer: a
Explanation: The ASCII characters for the remaining options are:
1 : 00110001
A : 01000001
, : 00101100.
81. The code where all successive numbers differ from their preceding number by single bit is __________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
Answer: d
Explanation: The code where all successive numbers differ from their preceding number by single bit is gray code. It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next. BCD Code is one in which decimal digits are represented by a group of 4-bits each, whereas, in Excess-3 Code, the decimal numbers are incremented by 3 and then written in their BCD format.
82. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
Answer: c
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.
83. How many AND gates are required to realize Y = CD + EF + G?
a) 4
b) 5
c) 3
d) 2
Answer: d
Explanation: To realize Y = CD + EF + G, two AND gates are required and two OR gates are required.
84. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
Answer: a
Explanation: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option will be 00.
85. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2
Answer: a
Explanation: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.
86. A universal logic gate is one which can be used to generate any logic function. Which of the following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
Answer: d
Explanation: An Universal Logic Gate is one which can generate any logic function and also the three basic gates: AND, OR and NOT. Thus, NOR and NAND can generate any logic function and are thus Universal Logic Gates.
87. A full adder logic circuit will have __________
a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
Answer: d
Explanation: A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there. In case of half adder circuit, there are only two inputs bits and two outputs (SUM and CARRY).
88. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
Answer: a
Explanation: There are three product terms. So, three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.
89. Which of the following are known as universal gates?
a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR
Answer: a
Explanation: The NAND & NOR gates are known as universal gates because any digital circuit can be realized completely by using either of these two gates, and also they can generate the 3 basic gates AND, OR and NOT.
90. The gates required to build a half adder are __________
a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
Answer: c
Explanation: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR outputs the SUM of the two input bits whereas AND outputs the CARRY of the two input bits.
91. A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates
Answer: c
Explanation: A transistor can be used as a switch. That is when base is low collector is high (input zero, output one) and base is high collector is low (input 1, output 0).
92. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16
Answer: d
Explanation: For 4 inputs: 24 = 16 truth table entries are necessary.
93. Which input values will cause an AND logic gate to produce a HIGH output?
a) At least one input is HIGH
b) At least one input is LOW
c) All inputs are HIGH
d) All inputs are LOW
Answer: c
Explanation: For AND gate, the output is high only when both inputs are high. That’s why the high output in AND will occurs only when all the inputs are high. However, in case of OR gate, if atleast one input is high, the output will be high.
94. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates
Answer: c
Explanation: Expression for XOR is: A.(B’)+(A’).B
So in the above expression, the following logic gates are used: AND, OR, NOT.
Thus, 2 AND gates with two-inputs and 1 OR gate with two-inputs will be required for constructing a XOR gate.
95. The basic logic gate whose output is the complement of the input is the ___________
a) OR gate
b) AND gate
c) INVERTER gate
d) XOR gate
Answer: c
Explanation: It is also called NOT gate and it simply inverts the input, such that 1 becomes 0 and 0 becomes 1.
96. The AND function can be used to ___________ and the OR function can be used to _____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert
Answer: a
Explanation: The AND gate and OR gate are used for enabling and disabling respectively because of their multiplicity and additivity property. The AND gate outputs 1 when all inputs are at logic 1, whereas the OR gate outputs 0 when all inputs are at logic 0.
97. The dependency notation “>=1” inside a block stands for which operation?
a) OR
b) XOR
c) AND
d) XNOR
Answer: a
Explanation: The dependency notation “>=1” inside a block stands for OR operation.
98. If we use an AND gate to inhibit a signal from passing one of the inputs must be ___________
a) LOW
b) HIGH
c) Inverted
d) Floating
Answer: a
Explanation: AND gate means A*B and OR gate means A+B and to inhibit means to get low signal, one of the input must be low. It means (0*1=0 or 1*0=0) we will get low output signal. Thus, AND gate outputs 1 only when all inputs are at logic level 1 else it outputs 0.
99. Logic gate circuits contain predictable gate functions that open theirs ____________
a) Outputs
b) Inputs
c) Pre-state
d) Impedance state
Answer: b
Explanation: Logic gate circuits contain predictable gate functions that open their inputs because we are free to give any types of inputs.
100. How many NAND circuits are contained in a 7400 NAND IC?
a) 1
b) 2
c) 4
d) 8
Answer: c
Explanation: 7400 IC’s pin has total 14 pin. Pin no 7 use for GND and pin no 14 used for +vcc and remaining pins used for connections. For a NAND gate two inputs are required and one output is obtained means for NAND gate 3 pin connections are required. Thus, a 7400IC contains 4 NAND gates with each having 3 pins. Therefore, total 12 pins dedicated for the NAND operation. Rest 2 pins for power supply.
101. The ______ format is usually used to store data.
a) BCD
b) Decimal
c) Hexadecimal
d) Octal
Answer: a
Explanation: The data usually used by computers have to be stored and represented in a particular format for ease of use.
102. The 8-bit encoding format used to store data in a computer is ______
a) ASCII
b) EBCDIC
c) ANCI
d) USCII
Answer: b
Explanation: The data to be stored in the computers have to be encoded in a particular way so as to provide secure processing of the data.
103. A source program is usually in _______
a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
Answer: c
Explanation: The program written and before being compiled or assembled is called as a source program.
104. Which memory device is generally made of semiconductors?
a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
Answer: a
Explanation: Memory devices are usually made of semiconductors for faster manipulation of the contents.
105. The small extremely fast, RAM’s are called as _______
a) Cache
b) Heaps
c) Accumulators
d) Stacks
Answer: a
Explanation: These small and fast memory devices are compared to RAM because they optimize the performance of the system and they only keep files which are required by the current process in them
106. The ALU makes use of _______ to store the intermediate results.
a) Accumulators
b) Registers
c) Heap
d) Stack
Answer: a
Explanation: The ALU is the computational center of the CPU. It performs all mathematical and logical operations. In order to perform better, it uses some internal memory spaces to store immediate results.
107. The control unit controls other units by generating ___________
a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
Answer: b
Explanation: This unit is used to control and coordinate between the various parts and components of the CPU.
108. ______ are numbers and encoded characters, generally used as operands.
a) Input
b) Data
c) Information
d) Stored Values
Answer: b
Explanation: None.
109. The Input devices can send information to the processor.
a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases
Answer: a
Explanation: The input devices use buffers to store the data received and when the buffer has some data it sends it to the processor.
110. ______ bus structure is usually used to connect I/O devices.
a) Single bus
b) Multiple bus
c) Star bus
d) Rambus
Answer: a
Explanation: BUS is a bunch of wires which carry address, control signals and data. It is used to connect various components of the computer.
111. The I/O interface required to connect the I/O device to the bus consists of ______
a) Address decoder and registers
b) Control circuits
c) Address decoder, registers and Control circuits
d) Only Control circuits
Answer: c
Explanation: The I/O devices are connected to the CPU via BUS and to interact with the BUS they have an interface.
112. To reduce the memory access time we generally make use of ______
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
Answer: d
Explanation: The time required to access a part of the memory for data retrieval.
113. ______ is generally used to increase the apparent size of physical memory.
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
Answer: b
Explanation: Virtual memory is like an extension to the existing memory.
114. MFC stands for ___________
a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command
Answer: b
Explanation: This is a system command enabled when a memory function is completed by a process.
115. The time delay between two successive initiations of memory operation _______
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay
Answer: c
Explanation: The time is taken to finish one task and to start another.
1. In parts of the processor, adders are used to calculate ____________
a) Addresses
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned
Answer: d
Explanation: Adders are used to perform the operation of addition. Thus, in parts of the processor, adders are used to calculate addresses, table indices, increment and decrement operators, and similar operations.
2.Total number of inputs in a half adder is __________
a) 2
b) 3
c) 4
d) 1
Answer: a
Explanation: Total number of inputs in a half adder is two. Since, an EXOR gates has 2 inputs and carry is connected with the input of EXOR gates. The output of half-adder is also 2, them being, SUM and CARRY. The output of EXOR gives SUM and that of AND gives carry.
3.In which operation carry is obtained?
a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
Answer: b
Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is obtained after 1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 – 1 = 1 (borrow 1).
4.If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: c
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry is given by A AND B.
5.If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: a
Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while the sum is given by A XOR B.
6.Half-adders have a major limitation in that they cannot __________
a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
Answer: c
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multi-bit numbers. However, the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both being high.
7.The difference between half adder and full adder is __________
a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
d) All of the Mentioned
Answer: c
Explanation: Half adder has two inputs while full adder has three outputs; this is the difference between them, while both have two outputs SUM and CARRY.
8.If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
Answer: c
Explanation: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR C.
9.If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
Answer: a
Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B) AND C, which is equivalent to (A AND B) OR (B AND C) OR (C AND A).
10.How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Answer: b
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder, provided using half adder. Otherwise, configuration of full adder would require 3 AND, 2 OR and 2 EXOR.
11.What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output
Answer: b
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.
12.Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) DeMultiplexer
Answer: a
Explanation: Data Selector is another name of Multiplexer. A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.
13.It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of ___________
a) Inputs
b) Outputs
c) Selection lines
d) Enable lines
Answer: a
Explanation: It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of inputs.
14.Which is the major functioning responsibility of the multiplexing combinational circuit?
a) Decoding the binary information
b) Generation of all minterms in an output function with OR-gate
c) Generation of selected path between multiple sources and a single destination
d) Encoding of binary information
Answer: c
Explanation: The major functioning responsibility of the multiplexing combinational circuit is generation of selected path between multiple sources and a single destination because it makes the circuit too flexible. A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.
15.What is the function of an enable input on a multiplexer chip?
a) To apply Vcc
b) To connect ground
c) To active the entire chip
d) To active one half of the chip
Answer: c
Explanation: Enable input is used to active the chip, when enable is high the chip works (ACTIVE), when enable is low the chip does not work (MEMORY). However, Enable can be Active-High or Active-Low, indicating it is active either when it is connected to VCC or GND respectively.
16.One multiplexer can take the place of ___________
a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits
Answer: d
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines. Since many operational behaviour can be performed by using a multiplexer. Whereas, a combinational circuit is a combination of many logic gates which makes the circuit more complex.
17.A digital multiplexer is a combinational circuit that selects ___________
a) One digital information from several sources and transmits the selected one
b) Many digital information and convert them into one
c) Many decimal inputs and transmits the selected information
d) Many decimal outputs and accepts the selected information
Answer: a
Explanation: A digital multiplexer is a combinational circuit that selects one digital information from several sources and transmits the selected information on a single output line depending on the status of the select lines. That is why it is also known as a data selector.
18.In a multiplexer, the selection of a particular input line is controlled by ___________
a) Data controller
b) Selected lines
c) Logic gates
d) Both data controller and selected lines
Answer: b
Explanation: The selection of a particular input line is controlled by a set of selected lines in a multiplexer, which helps to select a particular input from several sources.
19.If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
a) 2
b) m
c) n
d) 2n
Answer: b
Explanation: If the number of n selected input lines is equal to 2^m then it requires m select lines to select one of m select lines.
20.How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
Answer: d
Explanation: 2n input lines, n control lines and 1 output line available for MUX. Here, 8 input lines mean 23 inputs. So, 3 control lines are possible. Depending on the status of the select lines, the input is selected and fed to the output.
21.Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input to Single Output
Answer: a
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For one input, the demultiplexer gives several outputs. That is why, it is called a data distributor.
22.Most demultiplexers facilitate which type of conversion?
a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. Demultiplexer converts single input into multiple outputs.
23.In 1-to-4 demultiplexer, how many select lines are required?
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. Therefore, for 1:4 demultiplexer, 2 select lines are required.
24.In a multiplexer the output depends on its ___________
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As the select input changes, the output of the multiplexer varies according to that input.
25. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this case n = 3 since 23 = 8.
26.How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a demultiplexer, which are 8.
27.Which IC is used for the implementation of 1-to-16 DEMUX?
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input
28.Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are directly connected to the other’s output. Such types of structure is called cross coupling and due to which latches remain in the latched condition.
29.One example of the use of an S-R flip-flop is as ___________
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise caused during the switching of electronic devices.
30.The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or Undefined State occurs at both S and R being at 1.
31.When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete). The J & K flip-flop has 4 stable states: Latch, Reset, Set and Toggle.
32.Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
Answer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid state at both inputs being 1.
33.A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross coupling means the output of second gate is fed to the input of first gate and vice-versa.
34.The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called sequential circuits. Unlike sequential circuits, if output depends only on the present state, then it’s known as combinational circuits.
35.Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since, the combinational circuits do not require memory elements whereas the sequential circuits need memory devices to perform their operations in sequence. Latches and Flip-flops come under sequential circuits.
36.How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock signal.
37.The sequential circuit is also called ___________
a) Flip-flop
b) Latch
c) Strobe
d) Adder
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of information.
38.The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the second output Q’ = 1 and vice versa.
39.In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
Answer: b
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.
40.The output of latches will remain in set/reset untill ___________
a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change the state.
41.A register is defined as ___________
a) The group of latches for storing one bit of information
b) The group of latches for storing n-bit of information
c) The group of flip-flops suitable for storing one bit of information
d) The group of flip-flops suitable for storing binary information
Answer: d
Explanation: A register is defined as the group of flip-flops suitable for storing binary information. Each flip-flop is a binary cell capable of storing one bit of information. The data in a register can be transferred from one flip-flop to another.
42.The register is a type of ___________
a) Sequential circuit
b) Combinational circuit
c) CPU
d) Latches
Answer: a
Explanation: Register’s output depends on the past and present states of the inputs. The device which follows these properties is termed as a sequential circuit. Whereas, combinational circuits only depend on the present values of inputs.
43.How many types of registers are?
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: There are 4 types of shift registers, viz., Serial-In/Serial-Out, Serial-In/Parallel-Out, Parallel-In/Serial-Out and Parallel-In/Parallel-Out.
44.The main difference between a register and a counter is ___________
a) A register has no specific sequence of states
b) A counter has no specific sequence of states
c) A register has capability to store one bit of information but counter has n-bit
d) A register counts data
Answer: a
Explanation: The main difference between a register and a counter is that a register has no specific sequence of states except in certain specialised applications.
45.In D register, ‘D’ stands for ___________
a) Delay
b) Decrement
c) Data
d) Decay
Answer: c
Explanation: D stands for “data” in case of flip-flops and not delay. Registers are made of a group of flip-flops.
50.Registers capable of shifting in one direction is ___________
a) Universal shift register
b) Unidirectional shift register
c) Unipolar shift register
d) Unique shift register
Answer: b
Explanation: The register capable of shifting in one direction is unidirectional shift register. The register capable of shifting in both directions is known as a bidirectional shift register.
51.A register that is used to store binary information is called ___________
a) Data register
b) Binary register
c) Shift register
d) D – Register
Answer: b
Explanation: A register that is used to store binary information is called a binary register. A register in which data can be shifted is called shift register.
52.A shift register is defined as ___________
a) The register capable of shifting information to another register
b) The register capable of shifting information either to the right or to the left
c) The register capable of shifting information to the right only
d) The register capable of shifting information to the left only
Answer: b
Explanation: The register capable of shifting information either to the right or to the left is termed as shift register. A register in which data can be shifted only in one direction is called unidirectional shift register, while if data can shifted in both directions, it is known as a bidirectional shift register.
53.How many methods of shifting of data are available?
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two types of shifting of data are available and these are serial shifting & parallel shifting.
54.In serial shifting method, data shifting occurs ____________
a) One bit at a time
b) simultaneously
c) Two bit at a time
d) Four bit at a time
Answer: a
Explanation: As the name suggests serial shifting, it means that data shifting will take place one bit at a time for each clock pulse in a serial fashion. While in parallel shifting, shifting will take place with all bits simultaneously for each clock pulse in a parallel fashion.
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