1. The ______ format is usually used to store data.
a) BCD
b) Decimal
c) Hexadecimal
d) Octal
Answer: a
Explanation: The data usually used by computers have to be stored and represented in a particular format for ease of use.
2. The 8-bit encoding format used to store data in a computer is ______
a) ASCII
b) EBCDIC
c) ANCI
d) USCII
Answer: b
Explanation: The data to be stored in the computers have to be encoded in a particular way so as to provide secure processing of the data.
3. A source program is usually in _______
a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
Answer: c
Explanation: The program written and before being compiled or assembled is called as a source program.
4. Which memory device is generally made of semiconductors?
a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
Answer: a
Explanation: Memory devices are usually made of semiconductors for faster manipulation of the contents.
5. The small extremely fast, RAM’s are called as _______
a) Cache
b) Heaps
c) Accumulators
d) Stacks
Answer: a
Explanation: These small and fast memory devices are compared to RAM because they optimize the performance of the system and they only keep files which are required by the current process in them
6. The ALU makes use of _______ to store the intermediate results.
a) Accumulators
b) Registers
c) Heap
d) Stack
Answer: a
Explanation: The ALU is the computational center of the CPU. It performs all mathematical and logical operations. In order to perform better, it uses some internal memory spaces to store immediate results.
7. The control unit controls other units by generating ___________
a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
Answer: b
Explanation: This unit is used to control and coordinate between the various parts and components of the CPU.
8. ______ are numbers and encoded characters, generally used as operands.
a) Input
b) Data
c) Information
d) Stored Values
Answer: b
Explanation: None.
9. The Input devices can send information to the processor.
a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases
Answer: a
Explanation: The input devices use buffers to store the data received and when the buffer has some data it sends it to the processor.
10. ______ bus structure is usually used to connect I/O devices.
a) Single bus
b) Multiple bus
c) Star bus
d) Rambus
Answer: a
Explanation: BUS is a bunch of wires which carry address, control signals and data. It is used to connect various components of the computer.
11. The I/O interface required to connect the I/O device to the bus consists of ______
a) Address decoder and registers
b) Control circuits
c) Address decoder, registers and Control circuits
d) Only Control circuits
Answer: c
Explanation: The I/O devices are connected to the CPU via BUS and to interact with the BUS they have an interface.
12. To reduce the memory access time we generally make use of ______
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
Answer: d
Explanation: The time required to access a part of the memory for data retrieval.
13. ______ is generally used to increase the apparent size of physical memory.
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
Answer: b
Explanation: Virtual memory is like an extension to the existing memory.
14. MFC stands for ___________
a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command
Answer: b
Explanation: This is a system command enabled when a memory function is completed by a process.
15. The time delay between two successive initiations of memory operation _______
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay
Answer: c
Explanation: The time is taken to finish one task and to start another.
16. The decoded instruction is stored in ______
a) IR
b) PC
c) Registers
d) MDR
Answer: a
Explanation: The instruction after obtained from the PC, is decoded and operands are fetched and stored in the IR.
17. The instruction -> Add LOCA, R0 does _______
a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
Answer: c
Explanation: None.
18. Which registers can interact with the secondary storage?
a) MAR
b) PC
c) IR
d) R0
Answer: a
Explanation: MAR can interact with secondary storage in order to fetch data from it.
19. During the execution of a program which gets initialized first?
a) MDR
b) IR
c) PC
d) MAR
Answer: c
Explanation: For the execution of a process first the instruction is placed in the PC.
20. Which of the register/s of the processor is/are connected to Memory Bus?
a) PC
b) MAR
c) IR
d) Both PC and MAR
Answer: b
Explanation: MAR is connected to the memory BUS in order to access the memory.
21. ISP stands for _________
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
Answer: a
Explanation: None.
22. The internal components of the processor are connected by _______
a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
Answer: b
Explanation: The processor BUS is used to connect the various parts in order to provide a direct connection to the CPU.
23. ______ is used to choose between incrementing the PC or performing ALU operations.
a) Conditional codes
b) Multiplexer
c) Control unit
d) None of the mentioned
Answer: b
Explanation: The multiplexer circuit is used to choose between the two as it can give different results based on the input.
24. The registers, ALU and the interconnection between them are collectively called as _____
a) process route
b) information trail
c) information path
d) data path
Answer: d
Explanation: The Operational and processing part of the CPU are collectively called as a data path.
25. _______ is used to store data in registers.
a) D flip flop
b) JK flip flop
c) RS flip flop
d) None of the mentioned
Answer: a
Explanation: None.
26. During the execution of the instructions, a copy of the instructions is placed in the ______
a) Register
b) RAM
c) System heap
d) Cache
Answer: d
Explanation: None.
27. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?
a) A
b) B
c) Both take the same time
d) Insufficient information
Answer: a
Explanation: The performance of a system can be found out using the Basic performance formula.
28. A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
d) None of the mentioned
Answer: b
Explanation: Pipe-lining is the process of improving the performance of the system by processing different instructions at the same time, with only one instruction performing one specific operation.
29. For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?
a) ISA
b) ANSA
c) Super-scalar
d) All of the mentioned
Answer: c
Explanation: In super-scalar architecture, the instructions are set in groups and they’re decoded and executed together reducing the amount of time required to process them.
30. The clock rate of the processor can be improved by _________
a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using the overclocking method
d) All of the mentioned
Answer: d
Explanation: The clock rate(frequency of the processor) is the hardware dependent quantity it is fixed for a given processor.
31. An optimizing Compiler does _________
a) Better compilation of the given piece of code
b) Takes advantage of the type of processor and reduces its process time
c) Does better memory management
d) None of the mentioned
Answer: b
Explanation: An optimizing compiler is a compiler designed for the specific purpose of increasing the operation speed of the processor by reducing the time taken to compile the program instructions.
32.. The ultimate goal of a compiler is to ________
a) Reduce the clock cycles for a programming task
b) Reduce the size of the object code
c) Be versatile
d) Be able to detect even the smallest of errors
Answer: a
Explanation: None.
33. SPEC stands for _______
a) Standard Performance Evaluation Code
b) System Processing Enhancing Code
c) System Performance Evaluation Corporation
d) Standard Processing Enhancement Corporation
Answer: c
Explanation: SPEC is a corporation that started to standardize the evaluation method of a system’s performance.
34. As of 2000, the reference system to find the performance of a system is _____
a) Ultra SPARC 10
b) SUN SPARC
c) SUN II
d) None of the mentioned
Answer: a
Explanation: In SPEC system of measuring a system’s performance, a system is used as a reference against which other systems are compared and performance is determined.
35.When Performing a looping operation, the instruction gets stored in the ______
a) Registers
b) Cache
c) System Heap
d) System stack
Answer: b
Explanation: When a looping or branching operation is carried out the offset value is stored in the cache along with the data.
36. The average number of steps taken to execute the set of instructions can be made to be less than one by following _______
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
Answer: c
Explanation: The number of steps required to execute a given set of instructions is sufficiently reduced by using super-scaling. In this method, a set of instructions are grouped together and are processed.
37. If a processor clock is rated as 1250 million cycles per second, then its clock period is ________
a) 1.9 * 10-10 sec
b) 1.6 * 10-9 sec
c) 1.25 * 10-10 sec
d) 8 * 10-10 sec
Answer: d
Explanation: None.
38. If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the value of S is (Where S is a term of the Basic performance equation)?
a) 3
b) ~2
c) ~1
d) 6
Answer: c
Explanation: S is the number of steps required to execute the instructions.
39. CISC stands for _______
a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
Answer: c
Explanation: CISC is a type of system architecture where complex instructions are grouped together and executed to improve system performance.
40. As of 2000, the reference system to find the SPEC rating are built with _____ Processor.
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
Answer: b
Explanation: None.
41.How many types of architectures are available, for designing a device that is able to work on its own?
a) 3
b) 2
c) 1
d) 4
Answer: b
Explanation: There are basically two main types of architectures present, they are Von Neumann and Harvard architectures.
42. Which architecture is followed by general purpose microprocessors?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: b
Explanation: General purpose microprocessors make use of Von Neumann architecture as here a simpler design is offered.
43.Which architecture involves both the volatile and the non volatile memory?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: In Harvard architecture, both the volatile and the non volatile memories are involved. This is done to increase its efficiency as both the memories are being used over here.
44.Which architecture provides separate buses for program and data memory?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
Answer: a
Explanation: Harvard Architecture provides separated buses for data and program memory to fetch program and data simultaneously. By doing this access time is reduced and hence performance is increased.
45.Which microcontroller doesn’t match with its architecture below?
a) Microchip PIC- Harvard
b) MSP430- Harvard
c) ARM7- Von Neumann
d) ARM9- Harvard
Answer: b
Explanation: MSP430 supports Von Neumann architecture.
46. Harvard architecture has _____________
a) dedicated buses for data and program memory
b) pipeline technique
c) complex architecture
d) all of the mentioned
Answer: d
Explanation: Harvard Architecture has dedicated buses for data and program memory and pipeline technique because of this architecture is complex.
47. Which out of the following supports Harvard architecture?
a) ARM7
b) Pentium
c) SHARC
d) All of the mentioned
Answer: c
Explanation: SHARC supports harvard architecture for signal processing in DSP.
48. Why most of the DSPs use Harvard architecture?
a) they provide greater bandwidth
b) they provide more predictable bandwidth
c) they provide greater bandwidth & also more predictable bandwidth
d) none of the mentioned
Answer: c
Explanation: Most of the DSPs use harvard architecture because they provide a wider predictable bandwidth.
49. Which of the following supports CISC as well as Harvard architecture?
a) ARM7
b) ARM9
c) SHARC
d) None of the mentioned
Answer: c
Explanation: SHARC supports both the CISC and the Harvard architecture.
50. Which of the two architecture saves memory?
a) Harvard
b) Von Neumann
c) Harvard & Von Neumann
d) None of the mentioned
Answer: b
Explanation: As only one memory is present in the Von Neumann architecture so it saves a lot of memory.
51. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
Answer: c
Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears in the form of successive byte or bytes.
52. The instruction, MOV AX, 1234H is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
Answer: c
Explanation: Since immediate data is present in the instruction.
53. The instruction, MOV AX, [2500H] is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
Answer: b
Explanation: Since the address is directly specified in the instruction as a part of it.
54. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
Answer: b
Explanation: Since register is used to refer the address.
55. The instruction, MOV AX,[BX] is an example of
a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
Answer: d
Explanation: Since the register used to refer to the address is accessed indirectly.
56. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
Answer: c
Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest of them, address is stored.
57. The addressing mode that is used in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
Answer: b
Explanation: In intrasegment indirect mode, the branch address is found as the content of a register or a memory location.
58. If the location to which the control is to be transferred lies in a different segment other than the current one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
Answer: d
Explanation: In intersegment mode, the control to be transferred lies in a different segment.
59. The instruction, JMP 5000H:2000H;
is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
Answer: c
Explanation: Since in intersegment direct mode, the address to which the control is to be transferred is in a different segment.
60. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
Answer: d
Explanation: The effective address is formed by adding the contents of both base and index registers to a default segment.
61. If a number of instructions are repeating through the main program, then to reduce the length of the program, __________ is used.
a) procedure
b) subroutine
c) macro
d) none of the mentioned
Answer: c
Explanation: For a certain number of instructions that are repeated in the main program, when macro is defined then the code of a program is reduced by placing the name of the macro at which the set of instructions are needed to be repeated.
62. The process of assigning a label or macroname to the string is called
a) initialising macro
b) initialising string macro
c) defining a string macro
d) defining a macro
Answer: d
Explanation: The process of assigning a label to the string is called defining a macro.
63. A macro within a macro is called
a) macro-within-macro
b) nested macro
c) macro-in-macro
d) none of the mentioned
Answer: b
Explanation: A macro may be called from inside a macro. This type of macro is called nested macro.
64. A macro can be defined as
a) beginning of a program
b) end of a program
c) after initialisation of program
d) anywhere in a program
Answer: d
Explanation: A macro can be defined anywhere in a program.
65. A macro can be used as ________
a) in data segment
b) to represent directives
c) to represent statements
d) all of the mentioned
Answer: d
Explanation: A macro may be used in data segment and can also be used to represent statements and directives.
66. The end of a macro can be represented by the directive.
a) END
b) ENDS
c) ENDM
d) ENDD
Answer: c
Explanation: The ENDM directive marks the end of the instructions or statements sequence assigned with the macro name.
67. Inserting the statements and instructions represented by macro, directly at the place of the macroname, in the program, is known as
a) calling a macro
b) inserting a macro
c) initializing a macro
d) none of the mentioned
Answer: a
Explanation: Inserting the statements and instructions at the place of macroname, in the program, is known as calling a macro.
68. The time required for execution of a macro is ________ that of the procedure.
a) greater than
b) less than
c) equal to
d) none of the mentioned
Answer: b
Explanation: The time required for execution of a macro is less than that of procedure as it does not contain CALL and RET instructions as the procedures do.
69. Which of the following statements is incorrect?
a) complete code of instruction string is inserted at each place, wherever the macroname appears
b) macro requires less time of execution than that of procedure
c) macro uses stack memory
d) macroname can be anything except registers and mnemonics
Answer: c
Explanation: Macro does not require stack memory and hence has less time for execution.
70. The beginning of the macro can be represented as
a) START
b) BEGIN
c) MACRO
d) None of the mentioned
Answer: c
Explanation: The beginning of the macro is represented as macroname followed by the directive MACRO.
SYNTAX: macroname MACRO
EXAMPLE: STRINGS MACRO.
71. The Stack follows the sequence
a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
Answer: c
Explanation: The stack follows last-in-first-out sequence.
72. If the processor is executing the main program that calls a subroutine, then after executing the main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned
Answer: b
Explanation: Since subroutine is called, to start the execution of the subroutine, the control is transferred to the subroutine address.
73. The stack is useful for
a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned
Answer: d
Explanation: Stack is used for temporary storage of contents of registers and memory locations, status of registers.
74. The Stack is accessed using
a) SP register
b) SS register
c) SP and SS register
d) None of the mentioned
Answer: c
Explanation: The stack is accessed using a pointer that is implemented using SP and SS registers.
75. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
Answer: d
Explanation: The data is stored from top address of the stack and is decremented by 2.
76. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2
Answer: b
Explanation: The data in the stack, may again be transferred back from a stack to register. At that time, the stack pointer is incremented by 2.
77. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
Answer: c
Explanation: The data is pushed into the stack while loading the stack.
78. The reverse process of transferring the data back from the stack to the CPU register is known as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
Answer: d
Explanation: The data retrieved from stack is called popping off.
79. The books arranged one on the other on a table is an example of
a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out
Answer: d
Explanation: If the books are arranged one on the other, then the book that is placed last will be the first out.
80. The PID temperature controller using 8086 has
a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack
Answer: d
Explanation: Since PID temperature controller has steps that need to be sequentially executed such as sampling the output, conversion of a signal with ADC, finding errors, deriving control signals and applying the control signal to control flow of energy.
81.Which of the following assembler directives are used to define a Procedure in the 8086 microprocessor?
a) PROCEDURE and ENDP
b) STARTP and ENDP
c) PROC and ENDPROC
d) None of the above
Answer: d. None of the above
82.Which of the following features is not offered by Macros?
a).Code reusability
b).Less memory space
c).Fast execution
d).None of the above
Answer: b. Less Memory Space
83.Which of the following is the correct syntax for calling a Macro?
a).MACRO macro_name
b).MACRO macro_name [ parameter’s list]
c).macro_name [parameter’s list ]
d).None of the above
Answer: c. macro_name [parameter’s list ]
84.Which of the following characteristics of Procedures makes it unfit for being used for short instruction sets with less number of instructions?
a).Extra code requirement for integrating procedures
b).Linking of procedures with the mainline program takes too much time
c).Extra work load on processor for shifting controls
d).All of the Above
Answer: d. All of the above
85.In a program, a Macro is being called ‘n’ times. Then how many times is the machine code generated for the same?
a).1 time
b).’n’ times
c).’n-1′ times
d).None of the above
Answer: b. ‘n’ times
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