1. The address space of the IA-32 is __________
a) 216
b) 232
c) 264
d) 28
Answer: b
Explanation: The number of addressable locations in
the memory is called as address space.
2. The addressing method used in IA-32 is ____________
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little and Big Endian
Answer: a
Explanation: The method of addressing the data in the
system.
3. The floating point numbers are stored in general
purpose register in IA-32.
a) True
b) False
Answer: b
Explanation: The floating registers are not stored in
general purpose registers as they have a real part and a decimal part.
4. The Floating point registers of IA-32 can operate
on operands up to ___________
a) 128 bit
b) 256 bit
c) 80 bit
d) 64 bit
Answer: d
Explanation: The size of the floating numbers that can
be stored in the floating register.
5. The size of the floating registers can be extended
upto _________
a) 128 bit
b) 256 bit
c) 80 bit
d) 64 bit
Answer: c
Explanation: None.
6. The IA-32 architecture associates different parts
of memory called __________ with different usages.
a) Frames
b) Pages
c) Tables
d) Segments
Answer: d
Explanation: The memory is divided into parts called
as segments.
7. The PC is incorporated with the help of general
purpose registers.
a) True
b) False
Answer: b
Explanation: Registers are not used to incorporate PC
as in other architectures, but a separate space is allocated to
it.
8. IOPL stands for ________
a) Input/Output Privilege level
b) Input Output Process Link
c) Internal Output Process Link
d) Internal Offset Privilege Level
Answer: a
Explanation: This indicates the security between the
transfers between the I/O devices and memory.
9. In IA-32 architecture along with the general flags,
the other conditional flags provided are ___________
a) IOPL
b) IF
c) TF
d) All of the mentioned
Answer: d
Explanation: These flags are basically used to check
the system for exceptions.
10. The register used to serve as PC is called as
___________
a) Indirection register
b) Instruction pointer
c) R-32
d) None of the mentioned
Answer: b
Explanation: The PC is used to store the next
instruction that is going to be executed.
11. The IA-32 processor can switch between 16 bit
operation and 32 bit operation with the help of instruction prefix bit.
a) True
b) False
Answer: a
Explanation: This switching enables a wide range of
operations to be performed.
12. The Bit extension of the register is denoted with
the help of __________ symbol.
a) $
b) `
c) E
d) ~
Answer: c
Explanation: This is used to extend the size of the
register.
13. The instruction, ADD R1, R2, R3 is decoded as
___________
a) R1<-[R1]+[R2]+[R3]
b) R3<-[R1]+[R2]
c) R3<-[R1]+[R2]+[R3]
d) R1<-[R2]+[R3]
Answer: d
Explanation: None.
14. The instruction JG loop does ______
a) jumps to the memory location loop if the result of
the most recent arithmetic op is even
b) jumps to the memory location loop if the result of
the most recent arithmetic op is greater than 0
c) jumps to the memory location loop if the test
condition is satisfied with the value of loop
d) none of the mentioned
Answer: b
Explanation: This instruction is used to cause a
branch based on the outcome of the arithmetic operation.
15. The LEA mnemonic is used to __________
a) Load the effective address of an instruction
b) Load the values of operands onto an accumulator
c) Declare the values as global constants
d) Store the outcome of the operation at a memory
location
Answer: a
Explanation: The effective address is the address of
the memory location required for the execution of the instruction.
16. ______ have been developed specifically for
pipelined systems.
a) Utility software
b) Speed up utilities
c) Optimizing compilers
d) None of the mentioned
Answer: c
Explanation: The compilers which are designed to
remove redundant parts of the code are called as optimizing compilers.
17. The pipelining process is also called as ______
a) Superscalar operation
b) Assembly line operation
c) Von Neumann cycle
d) None of the mentioned
Answer: b
Explanation: It is called so because it performs its
operation at the assembly level.
18. The fetch and execution cycles are interleaved
with the help of ________
a) Modification in processor architecture
b) Clock
c) Special unit
d) Control unit
Answer: b
Explanation: The time cycle of the clock is adjusted
to perform the interleaving.
19. Each stage in pipelining should be completed
within ___________ cycle.
a) 1
b) 2
c) 3
d) 4
Answer: a
Explanation: The stages in the pipelining should get
completed within one cycle to increase the speed of performance.
20. In pipelining the task which requires the least
time is performed first.
a) True
b) False
Answer: b
Explanation: This is done to avoid starvation of the
longer task.
21. If a unit completes its task before the allotted
time period, then _______
a) It’ll perform some other task in the remaining time
b) Its time gets reallocated to a different task
c) It’ll remain idle for the remaining time
d) None of the mentioned
Answer: c
Explanation: None.
22. To increase the speed of memory access in
pipelining, we make use of _______
a) Special memory locations
b) Special purpose registers
c) Cache
d) Buffers
Answer: c
Explanation: By using the cache we can reduce the
speed of memory access by a factor of 10.
23. The periods of time when the unit is idle is
called as _____
a) Stalls
b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
Answer: d
Explanation: The stalls are a type of hazards that
affect a pipelined system.
24. The contention for the usage of a hardware device
is called ______
a) Structural hazard
b) Stalk
c) Deadlock
d) None of the mentioned
Answer: a
Explanation: None.
25. The situation wherein the data of operands are not
available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
Answer: a
Explanation: Data hazards are generally caused when
the data is not ready on the destination side.
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