Intel 80386DX Processor

1. Which of the units is not a part of the internal architecture of 80386?

a) central processing unit

b) memory management unit

c) bus interface unit

d) none of the mentioned

Answer: d

Explanation: The internal architecture of 80386 is divided into three sections namely, central processing unit, memory management unit and bus interface unit.

 

2. The central processing unit has a sub-division of

a) memory unit and control unit

b) memory unit and ALU

c) execution unit and instruction unit

d) execution unit and memory unit

Answer: c

Explanation: The central processing unit is further divided into the execution unit and instruction unit.

 

3. The unit that is used for handling data, and calculates offset address is

a) memory management unit

b) execution unit

c) instruction unit

d) bus interface unit

Answer: b

Explanation: The execution unit has eight general purpose and eight special purpose registers, which are either used for handling the data or calculating the offset addresses.

 

4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is

a) memory management unit

b) execution unit

c) instruction unit

d) barrel shifter

Answer: c

Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction code queue, after decoding them so as to pass it to the control section, for deriving the necessary control signals.

 

5. The unit that increases the speed of all shift and rotate operations is

a) memory management unit

b) execution unit

c) instruction unit

d) barrel shifter

Answer: d

Explanation: The barrel shifter speeds up all shift and rotate operations.

 

6. The memory management unit consists of

a) segmentation unit

b) paging unit

c) segmentation and paging units

d) none of the mentioned

Answer: c

Explanation: The memory management unit consists of a segmentation unit and a paging unit.

 

7. The segmentation unit allows

a) maximum size of 4GB segments

b) use of segment address components

c) use of offset address components

d) all of the mentioned

Answer: d

Explanation: The segmentation unit allows the use of two address components. They are: segment and offset for relocation and sharing of code and data.

 

8. The unit that organizes the physical memory, in terms of pages of 4KB size each is

a) segmentation unit

b) execution unit

c) paging unit

d) instruction unit

Answer: c

Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.

 

9. The paging unit works under the control of

a) memory management unit

b) segmentation unit

c) execution unit

d) instruction unit

Answer: b

Explanation: The paging unit works under the control of the segmentation unit; i.e. each segment is further divided into pages.

 

10. The unit that provides a four level protection mechanism, for system’s code and data against application program is

a) central processing unit

b) segmentation unit

c) bus interface unit

d) none of the mentioned

Answer: b

Explanation: The segmentation unit provides a four level protection mechanism, for protecting and isolating the system’s code and data, from those of the application program.

 

11. The unit that has a prioritizer to resolve the priority of the various bus requests is

a) bus sizing unit

b) data buffer

c) bus control unit

d) execution unit

Answer: c

Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus requests.

 

12. The unit that interfaces the internal data bus with the system bus is

a) bus sizing unit

b) data buffer

c) bus control unit

d) execution unit

Answer: b

Explanation: The data buffer interfaces the internal data bus with the system bus.

 

13. The unit that drives the bus enable and address signals A0-A31 is

a) bus sizing unit

b) bus driving unit

c) address driver

d) bus driver

Answer: c

Explanation: The address driver drives the bus enable and address signals A0-A31.

 

14. Which of the following pin when activated, allows address pipelining?

a) ADS

b) NA

c) AP

d) None of the mentioned

Answer: b

Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus cycles.

 

15. The signal that is used to insert WAIT states in a bus cycle in 80386 is

a) HOLD

b) HLDA

c) READY

d) PEREQ

Answer: c

Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of slow devices with the CPU.

 

16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is

a) READY

b) NMI

c) HLDA

d) PEREQ

Answer: d

Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data word for the coprocessor.

 

17. The pipeline and dynamic bus sizing units handle

a) data signals

b) address signals

c) control signals

d) all of the mentioned

Answer: c

Explanation: The pipeline and dynamic bus sizing units handle the related control signals.

 

18. Which of the following is not a scale factor of addressing modes of 80386?

a) 2

b) 4

c) 6

d) 8

Answer: c

Explanation: In case of the scaled the modes, any of the index register values can be multiplied by a valid scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.

 

19. Contents of an index register are multiplied by a scale factor that may be added further to get the operand offset in

a) base scaled indexed mode

b) scaled indexed mode

c) indexed mode

d) none of the mentioned

Answer: b

Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale factor that may be added further to get the operand offset.

 

20. Contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset in

a) base scaled indexed mode

b) scaled indexed mode

c) indexed mode

d) none of the mentioned

Answer: a

Explanation: In base scaled indexed mode, contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset.

 

21. In the based scaled indexed mode with displacement mode, the contents of an index register are multiplied by a scale factor and are added to

a) base register

b) displacement

c) base register and displacement

d) none of the mentioned

Answer: c

Explanation: Contents of an index register are multiplied by a scale factor and the result is added to a base register and a displacement to get the offset of an operand.

 

22. The following statement of ALP is an example of

MOV EBX, [EDX*4] [ECX].

a) base scaled indexed mode

b) scaled indexed mode

c) indexed mode

d) based scaled indexed mode with displacement mode

Answer: a

Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset.

 

23. The following statement is an example of

MOV EBX, LIST [ESI*2].

MUL ECX, LIST [EBP*4].

a) base scaled indexed mode

b) scaled indexed mode

c) indexed mode

d) based scaled indexed mode with displacement mode

Answer: b

Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a scale factor that may be added further to get the operand offset.

 

24. Bit field can be defined as a group of

a) 8 bits

b) 16 bits

c) 32 bits

d) 64 bits

Answer: c

Explanation: A group of at the most 32 bits(4 bytes) is defined as a bit field.

 

25. The maximum length of the string in a bit string of contiguous bits is

a) 2 MB

b) 4 MB

c) 2 GB

d) 4 GB

Answer: d

Explanation: Bit string is a string of contiguous bits of maximum 4Gbytes in length.

 

26. The integer word is defined as

a) signed 8-bit data

b) unsigned 16-bit data

c) signed 16-bit data

d) signed 32-bit data

Answer: c

Explanation: The integer word is the signed 16-bit data.

 

27. A 16-bit displacement that references a memory location using any of the addressing modes is

a) Pointer

b) Character

c) BCD

d) Offset

Answer: d

Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using any of the addressing modes.

 

28. A decimal digit can be represented by

a) unsigned integer

b) signed integer

c) unpacked BCD

d) packed BCD

Answer: c

Explanation: Decimal digits from 0-9 are represented by unpacked bytes.

 

29. The 16-bit registers are available with their extended size of 32 bits, by adding the registers with a prefix of

a) X

b) E

c) 32

d) XX

Answer: b

Explanation: A 32 bit register, known as an extended register, is represented by the register name with a prefix of E.

 

30. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by

a) LSP

b) FSP

c) SP

d) None of the mentioned

Answer: c

Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the names BP, SP, SI and DI represent the lower 16-bits.

 

31. Which of the following is a data segment register of 80386?

a) ES

b) FS

c) GS

d) All of the mentioned

Answer: d

Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out of which DS, ES, FS and GS are the four data segment registers.

 

32. The register width used by the 32-bit addressing modes is

a) 8 bits

b) 16 bits

c) 32 bits

d) all of the mentioned

Answer: d

Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.

 

33. The flag that is additional in flag register of 80386, compared to that of 80286 is

a) VM flag

b) RF flag

c) VM and RF flag

d) None of the mentioned

Answer: c

Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag register of 80386.

 

34. The VM (virtual mode) flag is to be set, only when 80386 is in

a) virtual mode

b) protected mode

c) either virtual or protected mode

d) all of the mentioned

Answer: b

Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is to be set only when the 80386 is in protected mode.

 

35. In protected mode of 80386, the VM flag is set by using

a) IRET instruction

b) Task switch operation

c) IRET instruction or task switch operation

d) None of the mentioned

Answer: c

Explanation: The VM flag can be set using the IRET instruction or any task switch operation, only in the protected mode.

 

36. During the instruction cycle of 80386, any debug fault can be ignored if

a) VM flag is set

b) VM flag is cleared

c) RF is cleared

d) RF is set

Answer: d

Explanation: If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.

 

37. The RF is not automatically reset after the execution of

a) IRET

b) POPA

c) IRET and POPF

d) IRET and PUSHF

Answer: c

Explanation: The RF is automatically reset after the execution of every instruction, except for the IRET and POPF instructions. Also, it is not cleared automatically after the successful execution of JMP, CALL and INT instructions causing a task switch.

 

38. The segment descriptor register is used to store

a) attributes

b) limit address of segments

c) base address of segments

d) all of the mentioned

Answer: d

Explanation: The segment descriptor register is used to store the descriptor information like attributes, limit and base addresses of segments.

 

39. If the 80386 enters the protected mode from the real address mode, then it returns back to the real mode, by performing the operation of

a) read

b) write

c) terminate

d) reset

Answer: d

Explanation: If the 80386 enters the protected mode from the real address mode, then it cannot return back to the real mode without a reset operation.

 

40. The unit that is needed for virtual mode 80386, only to run the 8086 programs, which require more than 1 Mbyte of memory for memory management functions, is

a) execution unit

b) central processing unit

c) paging unit

d) segmentation unit

Answer: c

Explanation: Paging unit is not necessarily enabled in the virtual mode, but may be needed to run the 8086 programs, which require more than 1 Mbyte of memory, for memory management functions.

 

41. The number of pages that the paging unit allows, in the virtual mode of 80386 is

a) 64

b) 128

c) 256

d) 512

Answer: c

Explanation: In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size. Each of the pages may be located anywhere within the maximum 4Gbytes physical memory.

 

42. The privilege level at which the real mode programs are executed is

a) level 0

b) level 1

c) level 2

d) level 3

Answer: a

Explanation: The real mode programs are executed at the highest privilege level i.e. level 0.

 

43. The instructions to prepare the processor for protected mode can only be executed at the privilege level

a) level 0

b) level 1

c) level 2

d) level 3

Answer: a

Explanation: The instructions to prepare the processor for protected mode can only be executed at the level 0.

 

44. The instruction that is unable to set or read the VM (Virtual Mode) bit is

a) PUSHF

b) IRET

c) POPF

d) PUSHF and POPF

Answer: d

Explanation: The PUSHF and POPF instructions are unable to set or read the VM (Virtual Mode) bit, as they do not access it. The virtual mode can be entered by using IRET instruction.

 

45. If the CKM pin of 80387 is high, then 80387 is operated in

a) real address mode

b) protected mode

c) synchronous mode

d) asynchronous mode

Answer: c

Explanation: If the CKM pin of 80387 is high, then 80387 is operated in synchronous mode. If it is low, then 80387 is operated in asynchronous mode.

 

46. The unit that handles the data and directs it to either FIFO or instruction decoder depending on the bus control logic directive is

a) paging unit

b) central processing unit

c) segmentation unit

d) data interface and control unit

Answer: d

Explanation: The data interface and control unit handles the data, and direct it to either FIFO or instruction decoder, depending on the bus control logic directive.

 

47. The unit that is responsible for carrying out all the floating point calculations, allotted to the coprocessor by 80386, is

a) Central processing unit

b) ALU

c) FPU

d) None of the mentioned

Answer: c

Explanation: The FPU (floating point unit) is responsible for carrying out all the floating point calculations, allotted to the coprocessor by 80386.

 

48. The sizes of instruction and data pointer registers of 80387 respectively are

a) 32-bit, 32-bit

b) 48-bit, 32-bit

c) 32-bit, 48-bit

d) 48-bit, 48-bit

Answer: d

Explanation: 80387 consists of two 48-bit registers, known as instruction and data pointer registers.

 

49. To inform 80387 that the CPU wants to communicate with NPS1, the NPS1 line is directly connected to

a) A31

b) A30

c) M/IO

d) D31

Answer: c

Explanation: The NPS1 and NPS2 lines are directly connected with M/IO and A31 respectively, to inform 80387 that the CPU wants to communicate with it (NPS1), and it is using one of the reserved I/O addresses for 80387 (NPS2).